Compile cbmem.c instead of including it in romstage,

[coreboot.git] / src / mainboard / asus / m2v / romstage.c

diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 59b6c45bfc484b3d84f9263ef2fc2db8deac06d0..7c224632e146e6c19ab000eac2b7d8a9b3831a51 100644 (file)
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -44,8 +44,8 @@ unsigned int get_sbdn(unsigned bus);
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "superio/ite/it8712f/early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -56,21 +56,15 @@ unsigned int get_sbdn(unsigned bus);
 
 #define IT8712F_GPIO_BASE              0x0a20
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
 }
 
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-// defines S3_NVRAM_EARLY:
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -248,6 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        enable_rom_decode();
        m2v_bus_init();
        m2v_it8712f_gpio_init();
+       it8712f_enable_3vsbsw();
 
        printk(BIOS_INFO, "now booting... \n");