Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / asus / a8v-e_se / romstage.c

diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1f56947eed4a659d75ac620b5b24efaa00d1650b..393e560be504ac0bae0779bfbf4ad54d42122631 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -22,21 +22,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
-
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -59,11 +46,11 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -99,17 +86,12 @@ void soft_reset(void)
 
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-
-#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -170,11 +152,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
                // Node 0
-               (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-               (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
                // Node 1
-               (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-               (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
        };
        unsigned bsp_apicid = 0;
        int needs_reset = 0;
@@ -247,4 +229,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
        post_cache_as_ram();
 }
-