Remove comments that are obsolete since r6028.

[coreboot.git] / src / mainboard / asus / a8v-e_se / romstage.c

diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 7e9b6fc4dd0de07aaf3b60a14e3b7ebb5c3c0219..008a345d835c6bd8cc8e500ea89b916a56f4995e 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -5,7 +5,7 @@
  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
  * Copyright (C) 2006 MSI
  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> 
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,20 +22,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
-
 /* Used by init_cpus and fidvid */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>
@@ -44,10 +37,8 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -58,7 +49,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -67,10 +58,6 @@ unsigned int get_sbdn(unsigned bus);
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -80,16 +67,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-void activate_spd_rom(const struct mem_controller *ctrl)
+static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
+#include <reset.h>
 void soft_reset(void)
 {
        uint8_t tmp;
 
        set_bios_reset();
-       print_debug("soft reset \r\n");
+       print_debug("soft reset \n");
 
        /* PCI reset */
        tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -102,26 +90,22 @@ void soft_reset(void)
        }
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
+// defines S3_NVRAM_EARLY:
+#include "southbridge/via/k8t890/k8t890_early_car.c"
 
 #include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
+
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/via/k8t890/k8t890_early_car.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
-void hard_reset(void)
-{
-       print_info("NO HARD RESET. FIX ME!\n");
-}
-
 unsigned int get_sbdn(unsigned bus)
 {
        device_t dev;
@@ -131,7 +115,7 @@ unsigned int get_sbdn(unsigned bus)
        return (dev >> 15) & 0x1f;
 }
 
-void sio_init(void)
+static void sio_init(void)
 {
        u8 reg;
 
@@ -176,18 +160,17 @@ void sio_init(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
+               // Node 0
                (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
                (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+               // Node 1
                (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
                (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
-#endif
        };
        unsigned bsp_apicid = 0;
        int needs_reset = 0;
-       struct sys_info *sysinfo =
-           (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-       char *p;
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+               + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
        sio_init();
        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -195,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        console_init();
        enable_rom_decode();
 
-       print_info("now booting... fallback\r\n");
+       print_info("now booting... fallback\n");
 
        /* Is this a CPU only reset? Or is this a secondary CPU? */
        if (!cpu_init_detectedx && boot_cpu()) {
@@ -210,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        console_init();
        enable_rom_decode();
 
-       print_info("now booting... real_main\r\n");
+       print_info("now booting... real_main\n");
 
        if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -222,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        setup_coherent_ht_domain();
        wait_all_core0_started();
 
-       print_info("now booting... Core0 started\r\n");
+       print_info("now booting... Core0 started\n");
 
 #if CONFIG_LOGICAL_CPUS==1
        /* It is said that we should start core1 after all core0 launched. */
@@ -237,7 +220,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        needs_reset |= k8t890_early_setup_ht();
 
        if (needs_reset) {
-               print_debug("ht reset -\r\n");
+               print_debug("ht reset -\n");
                soft_reset();
        }
 
@@ -252,7 +235,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
        enable_smbus();
-       memreset_setup();
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
        post_cache_as_ram();
 }