amd southbirdge sb800 wrapper, pci bridge fix

[coreboot.git] / src / mainboard / asrock / e350m1 / devicetree.cb

diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 9dceae670095c7be66f3b7d4f50777b72fbc0dfa..bff8151fff9749a5ba6255b537c36efe51bd54b6 100644 (file)
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -16,17 +16,17 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
         device lapic_cluster 0 on
-                chip cpu/amd/agesa_wrapper/family14
+                chip cpu/amd/agesa/family14
                   device lapic 0 on end
                 end
         end
         device pci_domain 0 on
                 subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
 #                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
                                         device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
                                         device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                                         device pci 6.0 off end # PCIE P2P bridge 0x9606
                                         device pci 7.0 off end # PCIE P2P bridge 0x9607
                                         device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa_wrapper northbridge
+                                end # agesa northbridge
 
-                                chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
                                         device pci 11.0 on end # SATA
                                         device pci 12.0 on end # USB
                                         device pci 12.1 on end # USB
@@ -97,15 +97,23 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                                                        end
                                                end
                                        end #LPC
-                                       device pci 14.4 on end # PCI 0x4384
+                                       device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
                                        device pci 14.5 on end # USB 2
-                                       device pci 15.0 on end # PCIe PortA
-                                       device pci 15.1 on end # PCIe PortB
-                                       device pci 15.2 on end # PCIe PortC
-                                       device pci 15.3 on end # PCIe PortD
-                                       register "gpp_configuration" = "4" #1:1:1:1
-                                       register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-                               end     #southbridge/amd/cimx_wrapper/sb800
+                                       device pci 15.0 on  end # PCIe PortA
+                                       device pci 15.1 on  end # PCIe PortB: NIC
+                                       device pci 15.2 on  end # PCIe PortC: USB3
+                                       device pci 15.3 off end # PCIe PortD
+
+                                       # gpp_configuration options
+                                       #0000: PortA lanes[3:0]
+                                       #0001: N/A
+                                       #0010: PortA lanes[1:0], PortB lanes[3:2]
+                                       #0011: PortA lanes[1:0], PortB lane2, PortC lane3
+                                       #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
+                                       register "gpp_configuration" = "4"
+
+                                       register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
+                               end     #southbridge/amd/cimx/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary
                         device pci 18.0 on end
@@ -117,7 +125,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
                         device pci 18.5 on end
                         device pci 18.6 on end
                         device pci 18.7 on end
-                end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex