* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
#define RC0 (6<<8)
#define RC1 (7<<8)
-#define DIMM0 0x50
-#define DIMM1 0x51
-
#define SMBUS_HUB 0x71
#include <stdint.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
+#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+#include "superio/winbond/w83627dhg/early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
-#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
-
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_init(void)
pnp_enter_ext_func_mode(GPIO2345_DEV);
pnp_set_logical_device(GPIO2345_DEV);
- /* Pin 119 ~ 120 GP21, GP20 */
+ /* Pin 119 ~ 120 is GP21, GP20 */
reg = pnp_read_config(GPIO2345_DEV, 0x29);
pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
+ /* Turn on the Power LED ("Suspend LED" in Super I/O) */
+ reg = pnp_read_config(GPIO2345_DEV, 0xf3);
+ pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40));
+
/* todo document this */
pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
-
-//idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe
-//val 07 XX XX XX f6 0e 00 00 00 00 ff d6 96 00 40 d0 83 00 00 07
-
-//GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
-//mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
-//DDR voltage 44 45 46
-
- /* GPO20 - sideport voltage GPO23 - mgpuV */
+ /* GPO20 - sideport voltage 1 = 1.82 0 = 1.92
+ GPI21 - unknown input (NC?)
+ GPI22 - unknown input (NC?)
+ GPO23 - mgpuV bit0
+ GP24-27 - PS/2 mouse/keyb (only keyb is connected use flip interface for mouse)
+ */
pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
- /* GPO30 GPO33 GPO35 */
- //GPO35 - loadline control 0 - enabled
- //GPIO30 - unknown
- //GPIO33 - unknown
+ /* GPIO30 - unknown output, set to 0
+ GPI31 - unknown input NC?
+ GPI32 - unknown input NC?
+ GPIO33 - unknown output, set to 0.
+ GPI34 - unknown input NC?
+ GPO35 - loadline control 1 = enabled (2 phase clock) 0 = disabled 4 phase clock
+ GPIO36 - input = HT voltage 1.30V output (low) = HT voltage 1.35V
+ GP37 - unknown input NC? */
+
pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
- /* GPO40 GPO41 GPO42 GPO43 PO45 */
+ /* GPO40 - mgpuV bit2
+ GPO41 - mgpuV bit1
+ GPO42 - IRTX
+ GPO43 - IRRX
+ GPIO44 - memory voltage bit2 (input/outputlow)
+ GPIO45 - memory voltage bit1 (2.60 (000) - 2.95 (111))
+ GPIO46 - memory voltage bit0
+ GPIO47 - unknown input? */
+
pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
+ static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs780_dev8();
sb700_lpc_init();
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
post_cache_as_ram();
}
-
projects / coreboot.git / blobdiff