Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / artecgroup / dbe61 / romstage.c

diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 37cb71abd7e4cefd325e6c21106077adf7ae93a8..a8dc6cde59337daf140f0cf9115bb7aa8d5bb9f6 100644 (file)
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -33,7 +33,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -67,11 +66,6 @@ static int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_lx/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"
 
-static void mb_gpio_init(void)
-{
-       /* Early mainboard specific GPIO setup */
-}
-
 void main(unsigned long bist)
 {
        post_code(0x01);
@@ -97,7 +91,6 @@ void main(unsigned long bist)
        msr.lo |= 0x7 << 20;
        wrmsr(MDD_LEG_IO, msr);
 
-       mb_gpio_init();
        uart_init();
        console_init();
 
@@ -110,7 +103,7 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Dump memory configuratation */
+       /* Dump memory configuration. */
 #if 0
        msr = rdmsr(MC_CF07_DATA);
        print_debug("MC_CF07_DATA: ");
@@ -145,4 +138,3 @@ void main(unsigned long bist)
        // ram_check(0x00000000, 640 * 1024);
        // ram_check(1024 * 1024, 2 * 1024 * 1024);
 }
-