#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
-
+#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
static int spd_read_byte(unsigned device, unsigned address)
{
int i;
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
msr_t msr;
static const struct mem_controller memctrl[] = {
- {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+ {.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
- mb_gpio_init();
uart_init();
console_init();
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
- /* Dump memory configuratation */
+ /* Dump memory configuration. */
#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
// ram_check(0x00000000, 640 * 1024);
// ram_check(1024 * 1024, 2 * 1024 * 1024);
}
-