Use DIMM0 et al in lots more places instead of hardocding values.

[coreboot.git] / src / mainboard / artecgroup / dbe61 / romstage.c

diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index fea9925d373e69bcb3e421075ec0c3a45e122b45..37cb71abd7e4cefd325e6c21106077adf7ae93a8 100644 (file)
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -28,33 +25,25 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
-
-
-#define POST_CODE(x) outb(x, 0x80)
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
-
 static int spd_read_byte(unsigned device, unsigned address)
 {
        int i;
 
-       if (device == DIMM0){
-               for (i=0; i < (ARRAY_SIZE(spd_table)); i++){
-                       if (spd_table[i].address == address){
+       if (device == DIMM0) {
+               for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
+                       if (spd_table[i].address == address) {
                                return spd_table[i].data;
                        }
                }
@@ -76,51 +65,20 @@ static int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-       msr_t msr;
-       /* Setup access to the cache for under 1MB. */
-       msr.hi = 0x24fffc02;
-       msr.lo = 0x1000A000;    /* 0-A0000 write back */
-       wrmsr(CPU_RCONF_DEFAULT, msr);
-
-       msr.hi = 0x0;           /* write back */
-       msr.lo = 0x0;
-       wrmsr(CPU_RCONF_A0_BF, msr);
-       wrmsr(CPU_RCONF_C0_DF, msr);
-       wrmsr(CPU_RCONF_E0_FF, msr);
-
-       /* Setup access to the cache for under 640K. Note MC not setup yet. */
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU0 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU0 + 0x21, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU1 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU1 + 0x21, msr);
-
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
        /* Early mainboard specific GPIO setup */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
-       POST_CODE(0x01);
+       post_code(0x01);
 
+       msr_t msr;
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -134,19 +92,26 @@ void cache_as_ram_main(void)
         */
        /* cs5536_disable_internal_uart  disable them. Set them up now... */
        cs5536_setup_onchipuart(2); /* dbe61 uses UART2 as COM1 */
+       /* set address to 3F8 */
+       msr = rdmsr(MDD_LEG_IO);
+       msr.lo |= 0x7 << 20;
+       wrmsr(MDD_LEG_IO, msr);
+
        mb_gpio_init();
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
        /* Dump memory configuratation */
-       /*{
-       msr_t msr;
+#if 0
        msr = rdmsr(MC_CF07_DATA);
        print_debug("MC_CF07_DATA: ");
        print_debug_hex32(MC_CF07_DATA);
@@ -174,11 +139,10 @@ void cache_as_ram_main(void)
        print_debug_hex32(msr.lo);
        msr = rdmsr(MC_CF8F_DATA);
        print_debug(" \n");
-       }*/
+#endif
 
        /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
-       /* Memory is setup. Return to cache_as_ram.inc and continue to boot */
-       return;
+       // ram_check(0x00000000, 640 * 1024);
+       // ram_check(1024 * 1024, 2 * 1024 * 1024);
 }
+