Apply linuxbios-rename-other-payload-options.patch

[coreboot.git] / src / mainboard / amd / solo / Config.lb

diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb
index 7ce6031cbe5099d866b8bc33f72e222984e6d820..f7efc861ad63151344ef212a8beb1edc0b624043 100644 (file)
--- a/src/mainboard/amd/solo/Config.lb
+++ b/src/mainboard/amd/solo/Config.lb
@@ -15,12 +15,12 @@ end
 ## The linuxBIOS bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute where this copy of linuxBIOS will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
 ## Compute a range of ROM that can cached to speed up linuxBIOS,
@@ -42,6 +42,7 @@ driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 if HAVE_ACPI_TABLES object acpi_tables.o end
+#object reset.o
 
 ##
 ## Romcc output
@@ -144,7 +145,7 @@ chip northbridge/amd/amdk8/root_complex
                                                device pci 1.0 off end
                                        end
                                        device pci 1.0 on
-                                               chip superio/NSC/pc87360
+                                               chip superio/nsc/pc87360
                                                        device  pnp 2e.0 off  # Floppy 
                                                                 io 0x60 = 0x3f0
                                                                irq 0x70 = 6
@@ -199,6 +200,8 @@ chip northbridge/amd/amdk8/root_complex
                                        end
                                        device pci 1.5 off end
                                        device pci 1.6 on end
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
                                end
                        end #  device pci 18.0