//#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
-
-#define SET_NB_CFG_54 1
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-
+#include <lib.h>
+#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
-#endif
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
+static const u8 spd_addr[] = {
+ //first node
+ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+ // third node
+ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ // forth node
+ RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 4
+ RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 6
+ RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 8
+ RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 12
+ RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 16
+ RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 20
+ RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 24
+ RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+ RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 48
+ RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+ RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#endif
+};
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
-
}
-
projects / coreboot.git / blobdiff