Remove comments that are obsolete since r6028.

[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / romstage.c

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 8244746c1ed11cb9f628f94c29bf2e54eed66709..a908913cf4c1d4cae24c0f0a69ec1ed5827f361a 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -17,30 +17,19 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
 #define SYSTEM_TYPE 0  /* SERVER */
 //#define SYSTEM_TYPE 1        /* DESKTOP */
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
-
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
-
 #define SET_NB_CFG_54 1
 
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
 //used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -50,21 +39,12 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-/* FIXME: Use console.c post_code function */
-static void post_code(u8 value) {
-       outb(value, 0x80);
-}
-
-#include "arch/i386/lib/console.c"
-#include "pc80/serial.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -77,10 +57,9 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
 #endif
 #include "cpu/x86/bist.h"
 
-
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -93,12 +72,6 @@ static void memreset_setup(void)
        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
@@ -115,7 +88,6 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
        smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
 
-
 static int spd_read_byte(u32 device, u32 address)
 {
        int result;
@@ -124,26 +96,22 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
-
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 #include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -227,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
- #if FAM10_SET_FIDVID == 1
+ #if SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
@@ -250,7 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
  #endif
 
-
        /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
        if (!warm_reset_detect(0)) {
                print_info("...WARM RESET...\n\n\n");
@@ -260,7 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x3B);
 
-
        /* FIXME:  Move this to chipset init.
        enable cf9 for hard reset */
        print_debug("enable_cf9_x()\n");
@@ -272,12 +238,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
        post_code(0x3D);
 
-
        printk(BIOS_DEBUG, "enable_smbus()\n");
        enable_smbus();
        post_code(0x3E);
 
-
        memreset_setup();
        post_code(0x40);
 
@@ -287,7 +251,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        raminit_amdmct(sysinfo);
        post_code(0x41);
 
-
 /*
        dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
        dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
@@ -298,7 +261,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 //     ram_check(0x00200000, 0x00200000 + (640 * 1024));
 //     ram_check(0x40200000, 0x40200000 + (640 * 1024));
 
-
 //     die("After MCT init before CAR disabled.");
 
        post_code(0x42);
@@ -306,6 +268,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 
-
 }