/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
{
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
- int needs_reset = 0;
u32 bsp_apicid = 0;
u32 val;
msr_t msr;
post_code(0x30);
if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); //mmconf is inited in init_cpus
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
}
// Load MPB
val = cpuid_eax(1);
- printk_debug("Family_Model: %08x \n", val);
-
- /* FIXME: Need to make sure that APs are updated with the microcode and Errata */
- update_microcode(val);
- post_code(0x33);
-
- /* FIXME: This errata code needs to move out of the mainboard but I am not sure where to yet.*/
- /* FIXME: Check CPU revision to apply correct erratas */
- /* Rev B errata */
- /* Errata #169 - supercedes errata #131 */
- msr = rdmsr(0xC001001F);
- msr.hi |= 1 << (32 - 32);
- wrmsr(0xC001101F, msr);
-
- /* Errata #202 [DIS_PIGGY_BACK_SCRUB]=1 */
- msr = rdmsr(0xC0011022);
- msr.hi |= 1 << 24;
- wrmsr(0xC0010022, msr);
-
- /* 298 : FIXME: Fixed in B3/C1 */
-/* msr = rdmsr(0xC0010015);
- msr.lo |= 1 << 3;
- wrmsr(0xC0010015, msr);
-
- msr = rdmsr(0xC0011023);
- msr.lo |= 1 << 1;
- wrmsr(0xC0010023, msr);
-*/
- /* FIXME: Erratum #254 revB1 BU_CFG[21]=1 */
-
-
+ printk_debug("BSP Family_Model: %08x \n", val);
printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
- setup_mb_resource_map();
- post_code(0x34);
-
-// dump_pci_device(PCI_DEV(CBB, CDB, 0));
-
printk_debug("bsp_apicid = %02x \n", bsp_apicid);
printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
- post_code(0x35);
+ update_microcode(val);
+ post_code(0x33);
- // FIXME: Add needs_reset check to HT links.
- amd_ht_init(sysinfo);
-// print_pci_devices();
-// dump_pci_devices();
+ cpuSetAMDMSR();
+ post_code(0x34);
- post_code(0x36);
+ amd_ht_init(sysinfo);
+ post_code(0x35);
+ /* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
+ /* Setup any mainboard PCI settings etc. */
+ setup_mb_resource_map();
+ post_code(0x36);
+
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
It would be nice to fixup prink spinlocks for ROM XIP mode.
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
- // Core0 on each node is configured. Now setup any additional cores.
+ /* Core0 on each node is configured. Now setup any additional cores. */
printk_debug("start_other_cores()\n");
start_other_cores();
post_code(0x37);
#if FAM10_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
- printk_debug("Begin MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
post_code(0x39);
- if (warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ if (!warm_reset_detect(0)) { // BSP is node 0
+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- needs_reset |= (init_fidvid_bsp(bsp_apicid, sysinfo->nodes) << 31);
+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
}
post_code(0x3A);
- set_p0(); // Speed up the BSP!
-
- // show final fid and vid
+ /* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk_debug("End MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
- // Reset for HT and FIDVID changes?
- if (needs_reset) {
- print_info("\tht reset -\n");
+
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x3B);
- //enable cf9 for hard reset
+
+ /* FIXME: Move this to chipset init.
+ enable cf9 for hard reset */
print_debug("enable_cf9_x()\n");
enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x3C);
- //It's the time to set ctrl in sysinfo now;
+ /* It's the time to set ctrl in sysinfo now; */
printk_debug("fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x3D);
memreset_setup();
+ post_code(0x40);
// die("Die Before MCT init.");
- post_code(0x40);
printk_debug("raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
projects / coreboot.git / blobdiff