Update to the latest AMD Fam10 microcode patches.

[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Options.lb

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index cb68daa18175cbfbb681db99a5302461e7f517c5..ada80daff809bbe27d032ff135b79d18ae881833 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses TTYS0_BAUD
 uses TTYS0_BASE
@@ -114,6 +114,7 @@ uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CAR_FAM10
+uses AMD_UCODE_PATCH_FILE
 
 ###
 ### Build options
@@ -147,7 +148,7 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_FAILOVER_BOOT=1
 
 ##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
 ##
 default HAVE_HARD_RESET=1
 
@@ -174,7 +175,7 @@ default ACPI_SSDTX_NUM=31
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -260,11 +261,20 @@ default MAINBOARD_VENDOR="AMD"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
+##
+## Set microcode patch file name
+##
+##     Barcelona rev Ax:  "mc_patch_01000020.h"
+##     Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
+##     Barcelona rev B2, B3: "mc_patch_01000083.h"
+##
+default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
+
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -283,7 +293,7 @@ default HEAP_SIZE=0xc0000
 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00200000
 
@@ -334,7 +344,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately