Update equivalent processor revision ID to load latest microcode patches and

[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Options.lb

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index c06453c7001a2006ed54e2bc7c6ce8271499ad8e..80dff3a67a8df9b735d1f4bb1ef286b6f52d3e38 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -184,11 +184,10 @@ default LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
-## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
+default CONFIG_MAX_PHYSICAL_CPUS=8
+default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
 default CONFIG_LOGICAL_CPUS=1
 
 #default SERIAL_CPU_INIT=0
@@ -262,11 +261,12 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 ##
 ## Set microcode patch file name
 ##
-##     Barcelona rev Ax:  "mc_patch_01000020.h"
-##     Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
-##     Barcelona rev B2, B3: "mc_patch_01000083.h"
+##     Barcelona rev DR-Ax:  "mc_patch_01000020.h"
+##     Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
+##     Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
+##     Shanghai rev DA-C2: "mc_patch_0100009f.h"
 ##
-default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
+default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
 
 ###
 ### coreboot layout values