#
-# This file is part of the LinuxBIOS project.
+# This file is part of the coreboot project.
#
# Copyright (C) 2007 Advanced Micro Devices, Inc.
#
#
uses HAVE_MP_TABLE
+uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
+uses HAVE_ACPI_RESUME
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses USE_FAILOVER_IMAGE
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses CONFIG_USE_PRINTK_IN_CAR
uses CAR_FAM10
+uses AMD_UCODE_PATCH_FILE
###
### Build options
#FALLBACK: 512K - 4K
default FALLBACK_SIZE=0x7f000
#FAILOVER: 4k
-default FAILOVER_SIZE=0x01000
+default FAILOVER_SIZE=0x02000
#more 1M for pgtbl
#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
##
## Build code for SMP support
-## Only worry about 2 micro processors
##
default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
+default CONFIG_MAX_PHYSICAL_CPUS=8
+default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
default CONFIG_LOGICAL_CPUS=1
#default SERIAL_CPU_INIT=0
default APIC_ID_OFFSET=0x00
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+##
+## Set microcode patch file name
+##
+## Barcelona rev DR-Ax: "mc_patch_01000020.h"
+## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
+## Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
+## Shanghai rev DA-C2: "mc_patch_0100009f.h"
+##
+default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
+
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00200000
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
+#
+# CBFS
+#
+#
+default CONFIG_CBFS=0
end