#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include <reset.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-
#include "cpu/x86/bist.h"
-
#include "lib/delay.c"
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
-#define RC0 ((1<<0)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<2)<<8)
-#define RC3 ((1<<3)<<8)
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define RC0 ((1<<0)<<8)
+#define RC1 ((1<<1)<<8)
+#define RC2 ((1<<2)<<8)
+#define RC3 ((1<<3)<<8)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
};
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
+ if ((cpuid1.edx & 0x6) == 0x6) {
{
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
} else {
print_debug("Changing FIDVID not supported\n");
}
-
#endif
#if 1
#endif
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-