Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / amd / serengeti_cheetah / Kconfig

diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
index 3af08ec0460821e401cb4c3f2912172ae42a2802..6a4aea1abbd9681c237cbfd1708b1d6f724a7e4b 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -1,112 +1,97 @@
-config BOARD_AMD_SERENGETI_CHEETAH
-       bool "Serengeti Cheetah"
+if BOARD_AMD_SERENGETI_CHEETAH
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_F
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_AMD_AMD8111
        select SOUTHBRIDGE_AMD_AMD8131
        select SUPERIO_WINBOND_W83627HF
+       select BOARD_HAS_FADT
+       select HAVE_BUS_CONFIG
+       select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_PRINTK_IN_CAR
-       select USE_DCACHE_RAM
        select HAVE_HARD_RESET
-       select IOAPIC
        select LIFT_BSP_APIC_ID
-       select MEM_TRAIN_SEQ
-       select AP_CODE_IN_CAR
+       #select AP_CODE_IN_CAR
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select WAIT_BEFORE_CPUS_INIT
        select HAVE_ACPI_TABLES
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
        string
        default amd/serengeti_cheetah
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config DCACHE_RAM_BASE
        hex
        default 0xc8000
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config DCACHE_RAM_SIZE
        hex
        default 0x08000
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
        default 0x01000
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config APIC_ID_OFFSET
        hex
        default 0x8
-       depends on BOARD_AMD_SERENGETI_CHEETAH
-
-config LB_CKS_RANGE_END
-       int
-       default 122
-       depends on BOARD_AMD_SERENGETI_CHEETAH
-
-config LB_CKS_LOC
-       int
-       default 123
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config MAINBOARD_PART_NUMBER
        string
        default "Serengeti Cheetah"
-       depends on BOARD_AMD_SERENGETI_CHEETAH
-
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config MAX_CPUS
        int
        default 8
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config MAX_PHYSICAL_CPUS
        int
        default 4
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-       depends on BOARD_AMD_SERENGETI_CHEETAH
+config MEM_TRAIN_SEQ
+       int
+       default 1
 
 config SB_HT_CHAIN_ON_BUS0
        int
        default 2
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config HT_CHAIN_END_UNITID_BASE
        hex
        default 0x6
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config HT_CHAIN_UNITID_BASE
        hex
        default 0xa
-       depends on BOARD_AMD_SERENGETI_CHEETAH
-
-config USE_INIT
-       bool
-       default n
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config SERIAL_CPU_INIT
        bool
        default n
-       depends on BOARD_AMD_SERENGETI_CHEETAH
 
 config IRQ_SLOT_COUNT
        int
        default 11
-       depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+       hex
+       default 0x1022
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+       hex
+       default 0x2b80
+
+config ACPI_SSDTX_NUM
+       int
+       default 4
+
+endif # BOARD_AMD_SERENGETI_CHEETAH