* Explicitly add __PRE_RAM__ where it should be added.

[coreboot.git] / src / mainboard / amd / rumba / auto.c

diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index dae503b696aded08e52d18084509fb6a29a67ad7..1dce42548e36f07a7bc85db244a49fadeb821f21 100644 (file)
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -1,4 +1,5 @@
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -8,7 +9,7 @@
 #include <arch/hlt.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
+#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
@@ -16,8 +17,8 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
-#include "southbridge/amd/cs5535/cs5535_early_setup.c"
+#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
+#include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -93,7 +94,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 }
 
 #include "northbridge/amd/gx2/raminit.c"
-#include "sdram/generic_sdram.c"
+#include "lib/generic_sdram.c"
 
 #define PLLMSRhi 0x00001490
 #define PLLMSRlo 0x02000030
@@ -101,40 +102,20 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "cpu/amd/model_gx2/cpureginit.c"
-
+#include "cpu/amd/model_gx2/syspreinit.c"
 static void msr_init(void)
 {
+       /* total physical memory */
        __builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
 
+       /* traditional memory 0kB-512kB, 512kB-1MB */
        __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-        __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
-        __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
-        __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
-        __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
-
-        __builtin_wrmsr(0x10000080, 0x3, 0x0);
 
         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-       __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
-        __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
-        __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
-        __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
-
-        __builtin_wrmsr(0x50002001, 0x27, 0x0);
-        __builtin_wrmsr(0x4c002001, 0x1, 0x0);
-#if 1
-        __builtin_wrmsr(0x4c00000c, 0x0, 0x08);
-       __builtin_wrmsr(0x4c000016, 0x0, 0x0);
-       __builtin_wrmsr(0x4c00000c, 0x1, 0x0);
-       __builtin_wrmsr(0x4c00005e, 0x03880000, 0x00);
-       __builtin_wrmsr(0x4c00006f, 0x0000f000, 0x00);
-       __builtin_wrmsr(0x4c00005f, 0x08000000, 0x00);
-       __builtin_wrmsr(0x4c00000d, 0x82b5ad68, 0x80ad6b57);
-       __builtin_wrmsr(0x4c00000c, 0x0, 0x0);
-#endif
+
+       /* put code in northbridge[init].c here */
 }
 
 
@@ -144,13 +125,14 @@ static void main(unsigned long bist)
                {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
        };
 
-       msr_init();
+       SystemPreInit();
+       
 
-       w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 
-       cs5535_early_setup();
+       cs5536_early_setup();
 
        pll_reset();
 
@@ -159,7 +141,8 @@ static void main(unsigned long bist)
        
        sdram_initialize(1, memctrl);
 
-       
+       msr_init();
+
        /* Check all of memory */
        //ram_check(0x00000000, 640*1024);
 }