Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings.

[coreboot.git] / src / mainboard / amd / pistachio / romstage.c

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 8184cb29a23e3b2395e85ac55df1b53d838301ed..a3909f47995ff2bc2d82d102195f8312fb7c39e0 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -17,11 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
@@ -37,12 +34,8 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-
-#define post_code(x) outb(x, 0x80)
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
@@ -53,7 +46,12 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -62,7 +60,7 @@
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -87,7 +85,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -124,8 +122,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sb600_lpc_init();
 
        /* Pistachio used a FPGA to enable serial debug instead of a SIO
-        * and it doens't require any special setup. */
+        * and it doesn't require any special setup. */
        uart_init();
+
+#if CONFIG_USBDEBUG
+       sb600_enable_usbdebug(0);
+       early_usbdebug_init();
+#endif
+
        console_init();
 
        post_code(0x03);
@@ -186,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x06);
 
        if (needs_reset) {
-               print_info("ht reset -\r\n");
+               print_info("ht reset -\n");
                soft_reset();
        }
 
@@ -208,3 +212,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
+