#define ADT7475_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
-unsigned long uma_memory_start, uma_memory_size;
+uint64_t uma_memory_base, uma_memory_size;
/********************************************************
* pistachio uses a BCM5787 as on-board NIC.
{
u8 byte;
- printk_info("enable_onboard_nic.\n");
+ printk(BIOS_INFO, "%s.\n", __func__);
/* enable GPM8 output */
byte = pm_ioread(0x95);
u16 word;
u32 dword;
device_t sm_dev;
- struct bus pbus;
/* set adt7475 */
ADT7475_write_byte(0x40, 0x04);
/* remote 1 temperature offset */
ADT7475_write_byte(0x70, 0x00);
- printk_info("Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
+ printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
byte2, byte);
/* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
/* GPM5 as GPIO not USB OC */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword =
- pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x64);
+ dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 19;
- pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x64, dword);
+ pci_write_config32(sm_dev, 0x64, dword);
/* Enable Client Management Index/Data registers */
- dword =
- pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x78);
+ dword = pci_read_config32(sm_dev, 0x78);
dword |= 1 << 11; /* Cms_enable */
- pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x78, dword);
+ pci_write_config32(sm_dev, 0x78, dword);
/* MiscfuncEnable */
- byte =
- pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x41);
+ byte = pci_read_config8(sm_dev, 0x41);
byte |= (1 << 5);
- pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x41, byte);
+ pci_write_config8(sm_dev, 0x41, byte);
/* set GPM5 as input */
/* set index register 0C50h to 13h (miscellaneous control) */
pm2_iowrite(0x42, byte);
/* set GPIO 64 to input */
- word =
- pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x56);
+ word = pci_read_config16(sm_dev, 0x56);
word |= 1 << 7;
- pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.u.pci.devfn, 0x56, word);
+ pci_write_config16(sm_dev, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
*************************************************/
void pistachio_enable(device_t dev)
{
- struct mainboard_amd_pistachio_config *mainboard =
- (struct mainboard_amd_pistachio_config *)dev->chip_info;
+ struct mainboard_config *mainboard =
+ (struct mainboard_config *)dev->chip_info;
- printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev);
+ printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
msr = rdmsr(TOP_MEM);
- printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
__func__, msr.lo, msr.hi);
/* TOP_MEM2: the top of DRAM above 4G */
msr2 = rdmsr(TOP_MEM2);
- printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
switch (msr.lo) {
break;
}
- uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
- printk_info("%s: uma size 0x%08x, memory start 0x%08x\n",
- __func__, uma_memory_size, uma_memory_start);
+ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+ __func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */
#else
uma_memory_size = 0x8000000; /* 128M recommended UMA */
- uma_memory_start = 0x38000000; /* 1GB system memory supposed */
+ uma_memory_base = 0x38000000; /* 1GB system memory supposed */
#endif
enable_onboard_nic();
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
- printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
- uma_memory_start, uma_memory_size);
+ printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
+ uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
- uma_memory_start, uma_memory_size);
+ uma_memory_base, uma_memory_size);
#endif
}
-/*
-* CONFIG_CHIP_NAME defined in Option.lb.
-*/
-struct chip_operations mainboard_amd_pistachio_ops = {
+struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Pistachio Mainboard")
.enable_dev = pistachio_enable,
};
projects / coreboot.git / blobdiff