Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / amd / pistachio / Kconfig

diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig
index 1ce9fd1a140ba4819bd3aa7b6e956f19bff88853..b9f37b318861dd400b1f05878c242e24292f27f4 100644 (file)
--- a/src/mainboard/amd/pistachio/Kconfig
+++ b/src/mainboard/amd/pistachio/Kconfig
@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_AM2
+       select DIMM_DDR2
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_AMD_RS690
@@ -13,12 +14,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_DCACHE_RAM
        select HAVE_HARD_RESET
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select WAIT_BEFORE_CPUS_INIT
        select HAVE_ACPI_TABLES
        select BOARD_ROMSIZE_KB_1024
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string
@@ -44,10 +47,6 @@ config MAINBOARD_PART_NUMBER
        string
        default "Pistachio"
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 2
@@ -56,10 +55,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 1
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config SB_HT_CHAIN_ON_BUS0
        int
        default 1