Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / amd / norwich / romstage.c

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index e19b8ac257e07a7b374c22c9c705e1e12d6adf64..a9510d7543f3af2041ed7a99a06b196b12c8d962 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -19,19 +19,18 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
+#include <spd.h>
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -43,8 +42,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490    /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
@@ -64,7 +61,7 @@ void main(unsigned long bist)
        post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -78,7 +75,7 @@ void main(unsigned long bist)
        /* cs5536_disable_internal_uart: disable them for now, set them
         * up later...
         */
-       /* If debug. real setup done in chipset init via Config.lb. */
+       /* If debug. real setup done in chipset init via devicetree.cb. */
        cs5536_setup_onchipuart(1);
        mb_gpio_init();
        uart_init();
@@ -89,7 +86,7 @@ void main(unsigned long bist)
 
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
@@ -99,4 +96,3 @@ void main(unsigned long bist)
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }
-