Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / amd / norwich / romstage.c

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 1cc020fd416a1f26e4fcd5f2422f5900b623f976..8d108b3d89dc312d9e6b815523272ba4f7609cd5 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -19,18 +19,18 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
+#include <spd.h>
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -42,8 +42,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490    /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
@@ -53,17 +51,12 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/model_lx/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"
 
-static void mb_gpio_init(void)
-{
-       /* Early mainboard specific GPIO setup. */
-}
-
 void main(unsigned long bist)
 {
        post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -77,9 +70,8 @@ void main(unsigned long bist)
        /* cs5536_disable_internal_uart: disable them for now, set them
         * up later...
         */
-       /* If debug. real setup done in chipset init via Config.lb. */
+       /* If debug. real setup done in chipset init via devicetree.cb. */
        cs5536_setup_onchipuart(1);
-       mb_gpio_init();
        uart_init();
        console_init();
 
@@ -88,7 +80,7 @@ void main(unsigned long bist)
 
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
@@ -98,4 +90,3 @@ void main(unsigned long bist)
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }
-