* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
-
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
-
-#define SET_NB_CFG_54 1
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-/* FIXME: Use console.c post_code function */
-static void post_code(u8 value) {
- outb(value, 0x80);
-}
-
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-#include "arch/i386/lib/console.c"
-#include "pc80/serial.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
-
+#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
-#endif
-#define printk_info(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
#include "cpu/x86/bist.h"
-
-
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
-static int smbus_read_byte(u32 device, u32 address);
-
-#include "superio/ite/it8718f/it8718f_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "superio/ite/it8718f/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
+#include <spd.h>
-static void memreset_setup(void)
-{
-}
-
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
-#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
+#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
-#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
-
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
+#include "cpu/amd/microcode/microcode.c"
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
+#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- int last_boot_normal_flag = last_boot_normal();
-
- /* Is this a cpu only reset? or Is this a secondary cpu? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal_flag) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- /* mov bsp to bus 0xff when > 8 nodes */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
-
- sb700_pci_port80();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal_flag) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
-
-normal_image:
- __asm__ volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- );
-
-fallback_image:
- #if CONFIG_HAVE_FAILOVER_BOOT==1
- __asm__ volatile ("jmp __fallback_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- )
- #endif
- ;
-}
-#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */
-
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0.
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- #if CONFIG_USE_FAILOVER_IMAGE==1
- failover_process(bist, cpu_init_detectedx);
- #else
- real_main(bist, cpu_init_detectedx);
- #endif
-#else
- #if CONFIG_USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
- #endif
- real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
-//#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
-
-#define RC00 0
-#define RC01 1
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ /* mov bsp to bus 0xff when > 8 nodes */
+ set_bsp_node_CHtExtNodeCfgEn();
+ enumerate_ht_chain();
+ sb7xx_51xx_pci_port80();
+ }
+
post_code(0x30);
if (bist == 0) {
post_code(0x32);
enable_rs780_dev8();
- sb700_lpc_init();
+ sb7xx_51xx_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
- uart_init();
+
console_init();
- printk_debug("\n");
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
// Load MPB
val = cpuid_eax(1);
- printk_debug("BSP Family_Model: %08x \n", val);
- printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
- printk_debug("bsp_apicid = %02x \n", bsp_apicid);
- printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
+#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
+#endif
post_code(0x33);
cpuSetAMDMSR();
#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
- printk_debug("start_other_cores()\n");
+ printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
/* run _early_setup before soft-reset. */
rs780_early_setup();
- sb700_early_setup();
+ sb7xx_51xx_early_setup();
- #if FAM10_SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
rs780_htinit();
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
- printk_debug("fill_mem_ctrl()\n");
+ printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- post_code(0x3D);
- memreset_setup();
post_code(0x40);
// die("Die Before MCT init.");
- printk_debug("raminit_amdmct()\n");
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
- sb700_before_pci_init();
+ sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ * This routine is called every time a non-coherent chain is processed.
+ * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ * swap list. The first part of the list controls the BUID assignment and the
+ * second part of the list provides the device to device linking. Device orientation
+ * can be detected automatically, or explicitly. See documentation for more details.
+ *
+ * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ * based on each device's unit count.
+ *
+ * Parameters:
+ * @param[in] u8 node = The node on which this chain is located
+ * @param[in] u8 link = The link on the host for this chain
+ * @param[out] u8** list = supply a pointer to a list
+ * @param[out] BOOL result = true to use a manual list
+ * false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+ static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
+ /* If the BUID was adjusted in early_ht we need to do the manual override */
+ if ((node == 0) && (link == 0)) { /* BSP SB link */
+ *List = swaplist;
+ return 1;
+ }
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */
+ return 0;
+}
projects / coreboot.git / blobdiff