printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / mainboard / amd / mahogany_fam10 / romstage.c

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index ebb47f1cdc38164b75609ccd2fad9960db450117..d0d057c9d780f0c4d404b5a5586f2dbef4200d5b 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -58,14 +58,12 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -74,14 +72,12 @@ static void post_code(u8 value) {
 #if 0
 void die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
+#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
 #endif
-#define printk_info(fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
+#define printk(BIOS_INFO, fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
@@ -128,13 +124,10 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
-
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
 //#include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -181,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-       printk_debug("\n");
+       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
@@ -190,10 +183,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        // Load MPB
        val = cpuid_eax(1);
-       printk_debug("BSP Family_Model: %08x \n", val);
-       printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
-       printk_debug("bsp_apicid = %02x \n", bsp_apicid);
-       printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+       printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+       printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+       printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+       printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);
@@ -224,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  #if CONFIG_LOGICAL_CPUS==1
        /* Core0 on each node is configured. Now setup any additional cores. */
-       printk_debug("start_other_cores()\n");
+       printk(BIOS_DEBUG, "start_other_cores()\n");
        start_other_cores();
        post_code(0x37);
        wait_all_other_cores_started(bsp_apicid);
@@ -238,7 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
  #if FAM10_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
-       printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+       printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
        /* FIXME: The sb fid change may survive the warm reset and only
           need to be done once.*/
@@ -256,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);
-       printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+       printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
  #endif
 
        rs780_htinit();
@@ -271,7 +264,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x3B);
 
        /* It's the time to set ctrl in sysinfo now; */
-       printk_debug("fill_mem_ctrl()\n");
+       printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
        post_code(0x3D);
 
@@ -280,7 +273,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //     die("Die Before MCT init.");
 
-       printk_debug("raminit_amdmct()\n");
+       printk(BIOS_DEBUG, "raminit_amdmct()\n");
        raminit_amdmct(sysinfo);
        post_code(0x41);
 
@@ -301,10 +294,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sb700_before_pci_init();
 
        post_code(0x42);
-       printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+       printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 }
 
-
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */