Remove a few more warnings from fam10.

[coreboot.git] / src / mainboard / amd / mahogany_fam10 / romstage.c

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 3ae2d7663d3721770a68fdbd6697ab3b624d4478..17a0fd606f9dd3a9f5e1915c2ade0d609537914d 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -34,8 +34,8 @@
 #define FAM10_ALLOCATE_IO_RANGE 0
 
 //used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -71,14 +71,6 @@ static int smbus_read_byte(u32 device, u32 address);
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
@@ -99,8 +91,10 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
@@ -108,8 +102,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
 //#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
 
 #define RC00  0
 #define RC01  1
@@ -208,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if FAM10_SET_FIDVID == 1
+ #if SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
@@ -245,9 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* It's the time to set ctrl in sysinfo now; */
        printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-       post_code(0x3D);
 
-       memreset_setup();
        post_code(0x40);
 
 //     die("Die Before MCT init.");