Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / amd / mahogany / romstage.c

diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index f9ca92fac1d559ecc1ba3e8ce01fec7366a7915b..97a7aceeb2cad1e55683ee5d36a3d95a85b2a66a 100644 (file)
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -17,20 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
-#define QRANK_DIMM_SUPPORT 1
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
-#define ICS951462_ADDRESS      0x69
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -40,27 +29,20 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-
-#define post_code(x) outb(x, 0x80)
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include <usbdebug.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
@@ -87,16 +69,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-#include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -126,6 +102,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
+
+#if CONFIG_USBDEBUG
+       sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+       early_usbdebug_init();
+#endif
+
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -176,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
        if (needs_reset) {
-               print_info("ht reset -\r\n");
+               print_info("ht reset -\n");
                soft_reset();
        }
 
@@ -193,4 +175,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-