coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3

[coreboot.git] / src / mainboard / amd / dbm690t / mainboard.c

diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index ce206b951ec1ef50070c8297218bad785c8c8287..b60fb80b0ccb272c49695eb3c8933f82f81b7ded 100644 (file)
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -105,24 +105,24 @@ static void get_ide_dma66()
 
        byte =
            pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
-                               sm_dev->path.u.pci.devfn, 0xA9);
+                               sm_dev->path.pci.devfn, 0xA9);
        byte |= (1 << 5);       /* Set Gpio9 as input */
        pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
-                            sm_dev->path.u.pci.devfn, 0xA9, byte);
+                            sm_dev->path.pci.devfn, 0xA9, byte);
 
        ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
        byte =
            pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
-                               ide_dev->path.u.pci.devfn, 0x56);
+                               ide_dev->path.pci.devfn, 0x56);
        byte &= ~(7 << 0);
        if ((1 << 5) & pci_cf8_conf1.
-           read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn,
+           read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
                  0xAA))
                byte |= 2 << 0; /* mode 2 */
        else
                byte |= 5 << 0; /* mode 5 */
        pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
-                            ide_dev->path.u.pci.devfn, 0x56, byte);
+                            ide_dev->path.pci.devfn, 0x56, byte);
 }
 
 /*
@@ -158,10 +158,10 @@ static void set_thermal_config()
        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
        word =
            pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
-                                sm_dev->path.u.pci.devfn, 0x56);
+                                sm_dev->path.pci.devfn, 0x56);
        word |= 1 << 7;
        pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
-                             sm_dev->path.u.pci.devfn, 0x56, word);
+                             sm_dev->path.pci.devfn, 0x56, word);
 
        /* set GPIO 64 internal pull-up */
        byte = pm2_ioread(0xf0);