Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / amd / dbm690t / Kconfig

diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig
index 91a24bd3b770396c784209f38dd9d48b46f319d0..d1e2649f8a0f0dec450d3733d0be7af9c53359ae 100644 (file)
--- a/src/mainboard/amd/dbm690t/Kconfig
+++ b/src/mainboard/amd/dbm690t/Kconfig
@@ -10,39 +10,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select SOUTHBRIDGE_AMD_SB600
        select SUPERIO_ITE_IT8712F
        select BOARD_HAS_FADT
-       select GENERATE_ACPI_TABLES
-       select GENERATE_MP_TABLE
-       select GENERATE_PIRQ_TABLE
+       select HAVE_ACPI_TABLES
+       select HAVE_MP_TABLE
+       select HAVE_PIRQ_TABLE
        select HAVE_OPTION_TABLE
        select HAVE_MAINBOARD_RESOURCES
        select HAVE_BUS_CONFIG
-       select USE_DCACHE_RAM
        select HAVE_HARD_RESET
        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
        select BOARD_ROMSIZE_KB_1024
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select SET_FIDVID
 
 config MAINBOARD_DIR
        string
        default amd/dbm690t
 
-# This is a temporary fix, and should be removed when the race condition for
-# building option_table.h is fixed.
-config WARNINGS_ARE_ERRORS
-       bool
-       default n
-
-config DCACHE_RAM_BASE
-       hex
-       default 0xc8000
-
-config DCACHE_RAM_SIZE
-       hex
-       default 0x08000
-
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-       hex
-       default 0x01000
-
 config APIC_ID_OFFSET
        hex
        default 0x0
@@ -51,10 +35,6 @@ config MAINBOARD_PART_NUMBER
        string
        default "DBM690T"
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 2
@@ -63,10 +43,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 1
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config SB_HT_CHAIN_ON_BUS0
        int
        default 1