this should get the VIA VT8454c in shape with Kconfig

[coreboot.git] / src / mainboard / amd / dbm690t / Config.lb

diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb
index 9a3b6d93ad75c8cd3037d103d3b66319e1892d27..fde48a1cc2afddf5e33994aa4369782cf7f46ea5 100644 (file)
--- a/src/mainboard/amd/dbm690t/Config.lb
+++ b/src/mainboard/amd/dbm690t/Config.lb
@@ -33,13 +33,13 @@ driver mainboard.o
 
 #dir /drivers/si/3114
 
-if CONFIG_HAVE_MP_TABLE object mptable.o end
-if CONFIG_HAVE_PIRQ_TABLE
+if CONFIG_GENERATE_MP_TABLE object mptable.o end
+if CONFIG_GENERATE_PIRQ_TABLE
        object get_bus_conf.o
        object irq_tables.o
 end
 
-if CONFIG_HAVE_ACPI_TABLES
+if CONFIG_GENERATE_ACPI_TABLES
        object acpi_tables.o
        object fadt.o
        makerule dsdt.c
@@ -50,8 +50,6 @@ if CONFIG_HAVE_ACPI_TABLES
        object ./dsdt.o
 end
 
-#object reset.o
-
        if CONFIG_USE_INIT
 
                makerule ./cache_as_ram_auto.o
@@ -136,10 +134,9 @@ config chip.h
 #The variables belong to mainboard are defined here.
 
 #Define gpp_configuration,     A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#                                         1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#                      1: the system allows a PCIE link to be established on Dev2 or Dev3.
 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 #Define gfx_tmds, 0: didn't support TMDS, 1: support
@@ -158,10 +155,7 @@ chip northbridge/amd/amdk8/root_complex
                                chip southbridge/amd/rs690
                                        device pci 0.0 on end # HT      0x7910
                                        device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-                                               chip drivers/pci/onboard
-                                                       device pci 5.0 on end   # Internal Graphics 0x791F
-                                                       register "rom_address" = "0xfff00000"
-                                               end
+                                               device pci 5.0 on end   # Internal Graphics 0x791F
                                        end
                                        device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
                                        device pci 3.0 off end # PCIE P2P bridge        0x791b
@@ -170,7 +164,6 @@ chip northbridge/amd/amdk8/root_complex
                                        device pci 6.0 on end # PCIE P2P bridge 0x7916
                                        device pci 7.0 on end # PCIE P2P bridge 0x7917
                                        device pci 8.0 off end # NB/SB Link P2P bridge
-                                       register "vga_rom_address" = "0xfff00000"
                                        register "gpp_configuration" = "4"
                                        register "port_enable" = "0xfc"
                                        register "gfx_dev2_dev3" = "1"