Undo my ugly commit that added uses clauses in lots of places instead of one.

[coreboot.git] / src / mainboard / amd / db800 / Config.lb

diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb
index 5b35a06f1a9acd39a3731a51be47256b30be5e08..90525f32b085bc603b1705ffe464b1ced38e7fa4 100644 (file)
--- a/src/mainboard/amd/db800/Config.lb
+++ b/src/mainboard/amd/db800/Config.lb
@@ -1,38 +1,6 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE                   = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE         = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
 ## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
+default XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
 
 ##
 ## Set all of the defaults for an x86 architecture
@@ -50,16 +18,13 @@ if HAVE_PIRQ_TABLE
        object irq_tables.o
 end
 
-if USE_DCACHE_RAM
        #compile cache_as_ram.c to auto.inc
        makerule ./cache_as_ram_auto.inc
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
+                       action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
                        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
                        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
        end
-end
-
 
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
@@ -108,10 +73,8 @@ end
 ##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
 
-if USE_DCACHE_RAM
        mainboardinit cpu/amd/model_lx/cache_as_ram.inc
        mainboardinit ./cache_as_ram_auto.inc
-end
 
 ##
 ## Include the secondary Configuration files