amd southbirdge sb800 wrapper, pci bridge fix

[coreboot.git] / src / mainboard / advansus / a785e-i / devicetree.cb

diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb
index 74f50d02fa035adea32f2fdfcf5b846ffc53f7fe..79df8c90bd1b94e12664da3325d7e2acfd6af3b1 100644 (file)
--- a/src/mainboard/advansus/a785e-i/devicetree.cb
+++ b/src/mainboard/advansus/a785e-i/devicetree.cb
@@ -34,7 +34,7 @@ chip northbridge/amd/amdfam10/root_complex
                                        register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
                                        register "gfx_ddi_config" = "1"  # Lanes 0-3 DDI_SL
                                end
-                               chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus
+                               chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
                                        device pci 11.0 on end # SATA
                                        device pci 12.0 on end # USB
                                        device pci 12.2 on end # USB
@@ -98,7 +98,7 @@ chip northbridge/amd/amdfam10/root_complex
                                                         end
                                                 end     #superio/winbond/w83627hf
                                        end # LPC       0x439d
-                                       device pci 14.4 off end # PCI   0x4384 # PCI-b conflict with GPIO.
+                                       device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
                                        device pci 14.5 on end # USB 2
                                        device pci 14.6 off end # Gec
                                        device pci 15.0 on end # PCIe 0
@@ -112,7 +112,7 @@ chip northbridge/amd/amdfam10/root_complex
                                        #register "gpp_configuration" = "3" #2:1:1:0
                                        register "gpp_configuration" = "4" #1:1:1:1
                                        register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-                               end     #southbridge/amd/cimx_wrapper/sb800
+                               end     #southbridge/amd/cimx/sb800
                        end #  device pci 18.0
 
                        device pci 18.1 on end