- Update abuild.sh so it will rebuild successfull builds

[coreboot.git] / src / mainboard / Iwill / DK8S2 / auto.c

diff --git a/src/mainboard/Iwill/DK8S2/auto.c b/src/mainboard/Iwill/DK8S2/auto.c
index 6761646be1d97a279dafd9c47ea1681efd1984ff..9b40059e4386a75e0e88547ab919153ad8b894e3 100644 (file)
--- a/src/mainboard/Iwill/DK8S2/auto.c
+++ b/src/mainboard/Iwill/DK8S2/auto.c
@@ -2,10 +2,10 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
-#include <cpu/p6/apic.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -14,19 +14,21 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 static void hard_reset(void)
 {
-        set_bios_reset();
+       set_bios_reset();
 
        /* enable cf9 */
        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
@@ -40,6 +42,10 @@ static void soft_reset(void)
        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
 }
 
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
 static void memreset_setup(void)
 {
        if (is_cpu_pre_c0()) {
@@ -68,7 +74,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
        /* Routing Table Node i 
         *
         * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-        *  i:    0,    1,    2,    3,    4,    5,    6,    7
+        *  i:    0,    1,    2,    3,    4,    5,    6,    7
         *
         * [ 0: 3] Request Route
         *     [0] Route to this node
@@ -124,12 +130,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
 {
-       /*
-        * GPIO28 of 8111 will control H0_MEMRESET_L
-        * GPIO29 of 8111 will control H1_MEMRESET_L
-        */
        static const struct mem_controller cpu[] = {
 #if FIRST_CPU
                {
@@ -154,32 +156,39 @@ static void main(void)
                },
 #endif
        };
+
        int needs_reset;
-               
-       enable_lapic();
-       init_timer();
 
-       if (cpu_init_detected()) {
-               asm("jmp __cpu_reset");
+       if (bist == 0) {
+               /* Skip this if there was a built in self test failure */
+               amd_early_mtrr_init();
+               enable_lapic();
+               init_timer();
+               /* Has this cpu already booted? */
+               if (cpu_init_detected()) {
+                       asm volatile ("jmp __cpu_reset");
+               }
+               distinguish_cpu_resets();
+               if (!boot_cpu()) {
+                       stop_this_cpu();
+               }
        }
-       
-        distinguish_cpu_resets();
-       if (!boot_cpu()) {
-               stop_this_cpu();
-       }
-        
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       /* Setup the console */ 
+       w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        setup_default_resource_map();
        needs_reset = setup_coherent_ht_domain();
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+       needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
        if (needs_reset) {
                print_info("ht reset -\r\n");
                soft_reset();
        }
-               
+       
 #if 0
        print_pci_devices();
 #endif