Only BSP CPU writes CMOS in bootblock code

[coreboot.git] / src / lib / uart8250.c

diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index 49dc59105bc021cbd54d933f024f0f3b0c042202..b2246713cac087d03d4f010121219ace09eff13b 100644 (file)
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -21,6 +21,8 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <pc80/mc146818rtc.h>
+#include <trace.h>
+
 #if CONFIG_USE_OPTION_TABLE
 #include "option_table.h"
 #endif
@@ -48,7 +50,10 @@ void uart8250_tx_byte(unsigned base_port, unsigned char data)
 {
        uart8250_wait_to_tx_byte(base_port);
        outb(data, base_port + UART_TBR);
-       /* Make certain the data clears the fifos */
+}
+
+void uart8250_tx_flush(unsigned base_port)
+{
        uart8250_wait_until_sent(base_port);
 }
 
@@ -66,6 +71,7 @@ unsigned char uart8250_rx_byte(unsigned base_port)
 
 void uart8250_init(unsigned base_port, unsigned divisor)
 {
+       DISABLE_TRACE;
        /* Disable interrupts */
        outb(0x0, base_port + UART_IER);
        /* Enable FIFOs */
@@ -83,6 +89,7 @@ void uart8250_init(unsigned base_port, unsigned divisor)
 
        /* Set to 3 for 8N1 */
        outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+       ENABLE_TRACE;
 }
 
 void uart_init(void)
@@ -99,7 +106,7 @@ void uart_init(void)
        static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
        unsigned b_index = 0;
 #if defined(__PRE_RAM__)
-       b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
+       b_index = read_option(baud_rate, 0);
        b_index &= 7;
        div = divisor[b_index];
 #else