Add support to run SMM handler in TSEG instead of ASEG

[coreboot.git] / src / include / spd.h

diff --git a/src/include/spd.h b/src/include/spd.h
index b950f36f510c4db85bf32b55c64fe235952f2ea8..dfb0cc2bcc3259eeda1cb79acf8854f09cf4dea6 100644 (file)
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -73,6 +73,17 @@
 #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME      33 /* Command and address signal input hold time */
 #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME    34 /* Data signal input setup time */
 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME     35 /* Data signal input hold time */
+#define SPD_WRITE_RECOVERY_TIME             36 /* Write recovery time (tWR) */
+#define SPD_INT_WRITE_TO_READ_DELAY         37 /* Internal write to read command delay (tWTR) */
+#define SPD_INT_READ_TO_PRECHARGE_DELAY     38 /* Internal read to precharge command delay (tRTP) */
+#define SPD_MEM_ANALYSIS_PROBE_PARAMS       39 /* Memory analysis probe characteristics */
+#define SPD_BYTE_41_42_EXTENSION            40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
+#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH     41 /* Minimum active to active auto refresh (tRCmin) */
+#define SPD_MIN_AUTO_REFRESH_TO_ACT         42 /* Minimum auto refresh to active/auto refresh (tRFC) */
+#define SPD_MAX_DEVICE_CYCLE_TIME           43 /* Maximum device cycle time (tCKmax) */
+#define SPD_MAX_DQS_DQ_SKEW                 44 /* Maximum skew between DQS and DQ (tDQSQ) */
+#define SPD_MAX_READ_DATAHOLD_SKEW          45 /* Maximum read data-hold skew factor (tQHS) */
+#define SPD_PLL_RELOCK_TIME                 46 /* PLL relock time */
 #define SPD_SPD_DATA_REVISION_CODE          62 /* SPD data revision code */
 #define SPD_CHECKSUM_FOR_BYTES_0_TO_62      63 /* Checksum for bytes 0-62 */
 #define SPD_MANUFACTURER_JEDEC_ID_CODE      64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
@@ -129,6 +140,11 @@
 #define SPD_CAS_LATENCY_3_5              0x20
 #define SPD_CAS_LATENCY_4_0              0x40
 
+#define SPD_CAS_LATENCY_DDR2_3         (1 << 3)
+#define SPD_CAS_LATENCY_DDR2_4         (1 << 4)
+#define SPD_CAS_LATENCY_DDR2_5         (1 << 5)
+#define SPD_CAS_LATENCY_DDR2_6         (1 << 6)
+
 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 #define SPD_BURST_LENGTH_1               1
 #define SPD_BURST_LENGTH_2               2
@@ -140,5 +156,80 @@
 #define MODULE_BUFFERED                  1
 #define MODULE_REGISTERED                2
 
-#endif /* _SPD_H_ */
+/* DIMM SPD addresses */
+#define DIMM0                            0x50
+#define DIMM1                            0x51
+#define DIMM2                            0x52
+#define DIMM3                            0x53
+#define DIMM4                            0x54
+#define DIMM5                            0x55
+#define DIMM6                            0x56
+#define DIMM7                            0x57
+
+#define RC00 0
+#define RC01 1
+#define RC02 2
+#define RC03 3
+#define RC04 4
+#define RC05 5
+#define RC06 6
+#define RC07 7
+#define RC08 8
+#define RC09 9
+#define RC10 10
+#define RC11 11
+#define RC12 12
+#define RC13 13
+#define RC14 14
+#define RC15 15
+#define RC16 16
+#define RC17 17
+#define RC18 18
+#define RC19 19
+#define RC20 20
+#define RC21 21
+#define RC22 22
+#define RC23 23
+#define RC24 24
+#define RC25 25
+#define RC26 26
+#define RC27 27
+#define RC28 28
+#define RC29 29
+#define RC30 30
+#define RC31 31
+
+#define RC32 32
+#define RC33 33
+#define RC34 34
+#define RC35 35
+#define RC36 36
+#define RC37 37
+#define RC38 38
+#define RC39 39
+#define RC40 40
+#define RC41 41
+#define RC42 42
+#define RC43 43
+#define RC44 44
+#define RC45 45
+#define RC46 46
+#define RC47 47
+#define RC48 48
+#define RC49 49
+#define RC50 50
+#define RC51 51
+#define RC52 52
+#define RC53 53
+#define RC54 54
+#define RC55 55
+#define RC56 56
+#define RC57 57
+#define RC58 58
+#define RC59 59
+#define RC60 60
+#define RC61 61
+#define RC62 62
+#define RC63 63
 
+#endif