-/*\r
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $\r
- *\r
- * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register\r
- * \r
- *\r
- * Copyright (C) 2005 Digital Design Corporation\r
- *\r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
- *\r
- * $Log: sdram_mode.h,v $\r
- * Revision 1.1 2005/07/11 16:03:54 smagnani\r
- * Initial revision.\r
- *\r
- *\r
- */\r
-\r
-#ifndef __SDRAMMODE_H_DEFINED\r
-#define __SDRAMMODE_H_DEFINED\r
-\r
-// SDRAM Mode Register definitions, per JESD79D\r
-// These are transmitted via A0-A13\r
-\r
-// Burst length\r
-#define SDRAM_BURST_2 (1<<0)\r
-#define SDRAM_BURST_4 (2<<0)\r
-#define SDRAM_BURST_8 (3<<0)\r
-\r
-#define SDRAM_BURST_SEQUENTIAL (0<<3)\r
-#define SDRAM_BURST_INTERLEAVED (1<<3)\r
-\r
-#define SDRAM_CAS_2_0 (2<<4)\r
-#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */\r
-#define SDRAM_CAS_1_5 (5<<4) /* Optional */\r
-#define SDRAM_CAS_2_5 (6<<4)\r
-#define SDRAM_CAS_MASK (7<<4)\r
-\r
-#define SDRAM_MODE_NORMAL (0 << 7)\r
-#define SDRAM_MODE_TEST (1 << 7)\r
-#define SDRAM_MODE_DLL_RESET (2 << 7)\r
-\r
-// Extended Mode Register\r
-\r
-#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)\r
-#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)\r
-\r
-#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)\r
-#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */\r
-\r
-#endif // __SDRAMMODE_H_DEFINED\r
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
+ */
+
+#ifndef __SDRAMMODE_H_DEFINED
+#define __SDRAMMODE_H_DEFINED
+
+// SDRAM Mode Register definitions, per JESD79D
+// These are transmitted via A0-A13
+
+// Burst length
+#define SDRAM_BURST_2 (1<<0)
+#define SDRAM_BURST_4 (2<<0)
+#define SDRAM_BURST_8 (3<<0)
+
+#define SDRAM_BURST_SEQUENTIAL (0<<3)
+#define SDRAM_BURST_INTERLEAVED (1<<3)
+
+#define SDRAM_CAS_2_0 (2<<4)
+#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */
+#define SDRAM_CAS_1_5 (5<<4) /* Optional */
+#define SDRAM_CAS_2_5 (6<<4)
+#define SDRAM_CAS_MASK (7<<4)
+
+#define SDRAM_MODE_NORMAL (0 << 7)
+#define SDRAM_MODE_TEST (1 << 7)
+#define SDRAM_MODE_DLL_RESET (2 << 7)
+
+// Extended Mode Register
+
+#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
+#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
+
+#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
+#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
+
+#endif // __SDRAMMODE_H_DEFINED
projects / coreboot.git / blobdiff