#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
-#if defined( __ROMCC__) && !defined (__GNUC__)
+#if defined(__ROMCC__)
typedef __builtin_msr_t msr_t;
#else
-typedef struct msr_struct
+typedef struct msr_struct
{
unsigned lo;
unsigned hi;
} msr_t;
-static inline msr_t rdmsr(unsigned index)
+typedef struct msrinit_struct
+{
+ unsigned index;
+ msr_t msr;
+} msrinit_t;
+
+/* The following functions require the always_inline due to AMD
+ * function STOP_CAR_AND_CPU that disables cache as
+ * ram, the cache as ram stack can no longer be used. Called
+ * functions must be inlined to avoid stack usage. Also, the
+ * compiler must keep local variables register based and not
+ * allocated them from the stack. With gcc 4.5.0, some functions
+ * declared as inline are not being inlined. This patch forces
+ * these functions to always be inlined by adding the qualifier
+ * __attribute__((always_inline)) to their declaration.
+ */
+static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
{
msr_t result;
__asm__ __volatile__ (
return result;
}
-static inline void wrmsr(unsigned index, msr_t msr)
+static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
);
}
-#endif /* ROMCC__ && !__GNUC__ */
-
+#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */