#define CPU_L2TB_ENTRY 0x189E
#define CPU_L2TB_ENTRY_I 0x189F
#define CPU_DM_BIST 0x18C0
-
+
#define CPU_BC_CONF_0 0x1900
#define TSC_SUSP_SET (1<<5)
#define SUSP_EN_SET (1<<12)
-
+
#define CPU_BC_CONF_1 0x1901
#define CPU_BC_MSR_LOCK 0x1908
#define CPU_BC_L2_CONF 0x1920
#define CPU_CPUID12 0x3012
#define CPU_CPUID13 0x3013
-
+
/* VG GLIU0 port4*/
-
+
#define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
#define SMM_OFFSET 0x80400000 /* above 2GB */
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
-#if !defined(__ROMCC__) && !defined(ASSEMBLY)
+/* DRAM_TERMINATED affects how the DELAY register is set. */
+#define DRAM_TERMINATED 'T'
+#define DRAM_UNTERMINATED 't'
+/* Bitfield definitions for the DELAY register */
+#define DELAY_UPPER_DISABLE_CLK135 (1 << 23)
+#define DELAY_LOWER_STATUS_MASK 0x7C0
+
+#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
#if defined(__PRE_RAM__)
-void cpuRegInit(void);
+void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
void SystemPreInit(void);
#endif
void cpubug(void);