parser: refactor (von drei auf zwei prozess-modell)

[hwmod.git] / src / gen_pkg.vhd

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index c990f1b2f5354aa2c4670a9bcfbf53d310eb41ae..d97b94350ac47ac3d0dc1492805ea44497df84cb 100644 (file)
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -27,7 +27,6 @@ package gen_pkg is
        subtype hstring is string(1 to 72);
        subtype hstr_int is integer range 0 to 72;
 
-       function find_msb(a : std_logic_vector) return std_logic_vector;
        procedure icwait(signal clk_i : IN std_logic; cycles: natural);
 
        -- http://www.marjorie.de/ps2/scancode-set2.htm
@@ -42,64 +41,31 @@ package gen_pkg is
        constant SC_KP_8 : std_logic_vector(7 downto 0) := x"75";
        constant SC_KP_9 : std_logic_vector(7 downto 0) := x"7d";
 
+       constant SC_0 : std_logic_vector(7 downto 0) := x"45";
+       constant SC_1 : std_logic_vector(7 downto 0) := x"16";
+       constant SC_2 : std_logic_vector(7 downto 0) := x"1e";
+       constant SC_3 : std_logic_vector(7 downto 0) := x"26";
+       constant SC_4 : std_logic_vector(7 downto 0) := x"25";
+       constant SC_5 : std_logic_vector(7 downto 0) := x"2e";
+       constant SC_6 : std_logic_vector(7 downto 0) := x"36";
+       constant SC_7 : std_logic_vector(7 downto 0) := x"3d";
+       constant SC_8 : std_logic_vector(7 downto 0) := x"3e";
+       constant SC_9 : std_logic_vector(7 downto 0) := x"46";
+
        constant SC_KP_PLUS : std_logic_vector(7 downto 0) := x"79";
        constant SC_KP_MINUS : std_logic_vector(7 downto 0) := x"7b";
        constant SC_KP_MUL : std_logic_vector(7 downto 0) := x"7c";
        constant SC_KP_DIV : std_logic_vector(7 downto 0) := x"4a"; -- inkl. 0xe0!
 
+       -- fuer deutsches layout, alle anderen zeichen sind unguenstig belegt
+       constant SC_PLUS : std_logic_vector(7 downto 0) := x"5b";
+
        constant SC_ENTER : std_logic_vector(7 downto 0) := x"5a";
        constant SC_BKSP : std_logic_vector(7 downto 0) := x"66";
        constant SC_SPACE : std_logic_vector(7 downto 0) := x"29";
 end package gen_pkg;
 
 package body gen_pkg is
-       -- http://www.velocityreviews.com/forums/showpost.php?p=137148&postcount=5
-       function find_msb(a : std_logic_vector) return std_logic_vector is
-               function bits_to_fit(n : positive) return natural is
-                       variable nn, bits : natural := 0;
-               begin
-                       nn := n;
-                       while nn > 0 loop
-                               bits := bits + 1;
-                               nn := nn/2;
-                       end loop;
-                       return bits;
-               end;
-
-               function or_all(p : std_logic_vector) return std_logic is
-                       variable r : std_logic;
-               begin
-                       r := '0';
-                       for i in p'range loop
-                               r := r or p(i);
-                       end loop;
-                       return r;
-               end;
-
-               constant wN : positive := bits_to_fit(a'length - 1);
-               constant wP : positive := 2 ** wN;
-               variable pv : std_logic_vector(wP-1 downto 0);
-               variable n : std_logic_vector(wN downto 1);
-       begin
-               if a'length <= 2 then
-                       n(n'right) := a(a'left);
-               else
-                       pv(a'length-1 downto 0) := a;
-                       if or_all(pv(wP-1 downto wP/2)) = '1' then
-                               n := '1' & find_msb((pv(wP-1 downto wP/2)));
-                       else
-                               n := '0' & find_msb((pv(wP/2-1 downto 0)));
-                       end if;
-               end if;
-               return n;
-       end function find_msb;
-       -- -- alternativ: eleganter, braucht aber mehr logic cells
-       -- for i in (CBITS-1) downto 0 loop
-       --       exit when a(i) = '1';
-       --       r := r+1;
-       -- end loop;
-       -- return (CBITS - r);
-
        procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
        begin
                for i in 1 to cycles loop
@@ -107,4 +73,3 @@ package body gen_pkg is
                end loop;
        end;
 end package body gen_pkg;
-