* stevel@mvista.com or source@mvista.com
* Copyright (C) 2004 Tyan Computer.
* Auther: Yinghai Lu yhlu@tyan.com
- * move to LinuxBIOS
+ * move to coreboot
* This code is distributed without warranty under the GPL v2 (see COPYING) *
*/
#include <delay.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#if CONFIG_CONSOLE_BTEXT==1
+
+#define PLL_CRTC_DECODE 0
+#define SUPPORT_8_BPP_ABOVE 0
+
#include "fb.h"
#include "fbcon.h"
-#include "mach64.h"
struct aty_cmap_regs {
- u8 windex;
- u8 lut;
- u8 mask;
- u8 rindex;
- u8 cntl;
+ u8 windex;
+ u8 lut;
+ u8 mask;
+ u8 rindex;
+ u8 cntl;
};
-#include "atyfb.h"
-
#include <console/btext.h>
+#endif /*CONFIG_CONSOLE_BTEXT*/
+
+#include "mach64.h"
+
+#include "atyfb.h"
+
#include "mach64_ct.c"
#define MPLL_GAIN 0xad
#define VPLL_GAIN 0xd5
+#define HAS_VICTORIA 0
+
enum {
+#if HAS_VICTORIA==1
VICTORIA = 0,
XPERT98,
+#else
+ XPERT98=0,
+#endif
NUM_XL_CARDS
};
u8 dll2_cntl;
u8 pll_yclk_cntl;
} card_cfg[NUM_XL_CARDS] = {
+#if HAS_VICTORIA==1
// VICTORIA
{ 2700, SDRAM, 0x800000,
0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
0x82010102, 0x48803800, 0x005E0179,
0x50, 0x25
},
+#endif
// XPERT98
{ 1432, WRAM, 0x800000,
0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
info->ref_clk_per = 100000000UL/card->ref_crystal;
info->ram_type = card->mem_type;
info->total_vram = card->mem_size;
+#if HAS_VICTORIA == 1
if (xl_card == VICTORIA) {
// the MCLK, XCLK are 120MHz on victoria card
info->mclk_per = 1000000/120;
info->xclk_per = 1000000/120;
info->features &= ~M64F_MFB_TIMES_4;
}
+#endif
/*
* Calculate mclk and xclk dividers, etc. The passed
aty_st_le32(0xEC, 0x00000000, info);
aty_st_le32(0xFC, 0x00000000, info);
- for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
+ for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
}
static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
+
+#if CONFIG_CONSOLE_BTEXT==1
static void aty_set_crtc(const struct fb_info_aty *info,
const struct crtc *crtc);
static int aty_var_to_crtc(const struct fb_info_aty *info,
const struct fb_var_screeninfo *var,
struct crtc *crtc);
-#if 0
+#if PLL_CRTC_DECODE==1
static int aty_crtc_to_var(const struct crtc *crtc,
struct fb_var_screeninfo *var);
#endif
static int atyfb_decode_var(const struct fb_var_screeninfo *var,
struct atyfb_par *par,
const struct fb_info_aty *info);
-#if 0
+#if PLL_CRTC_DECODE==1
static int atyfb_encode_var(struct fb_var_screeninfo *var,
const struct atyfb_par *par,
const struct fb_info_aty *info);
#endif
-static void do_install_cmap(int con, struct fb_info *fb);
+static void do_install_cmap(int con, struct fb_info_aty *info);
#if 0
static u32 default_vram = 0;
#endif
struct fb_var_screeninfo default_var = {
- /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
- 640, 480, 640, 480, 0, 0, 8, 0,
- {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
- 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
- 0, FB_VMODE_NONINTERLACED
+ /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
+ 640, 480, 640, 480, 0, 0, 8, 0,
+ {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
+ 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
+ 0, FB_VMODE_NONINTERLACED
};
+#endif /*CONFIG_CONSOLE_BTEXT*/
+
static struct {
- u16 pci_id, chip_type;
- u8 rev_mask, rev_val;
- const char *name;
- int pll, mclk, xclk;
- u32 features;
+ u16 pci_id, chip_type;
+ u8 rev_mask, rev_val;
+ const char *name;
+ int pll, mclk, xclk;
+ u32 features;
} aty_chips[] = {
- /* 3D RAGE XL PCI-66/BGA */
- { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
- /* 3D RAGE XL PCI-33/BGA */
- { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
+ /* 3D RAGE XL PCI-66/BGA */
+ { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
+ /* 3D RAGE XL PCI-33/BGA */
+ { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
};
-#if 1
-static void aty_calc_mem_refresh(struct fb_info_aty *info,
- u16 id,
- int xclk)
+#if CONFIG_CONSOLE_BTEXT==1
+static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
{
int i, size;
#if 0
info->mem_refresh_rate = i;
}
-#endif
-static void ati_ragexl_init(device_t dev) {
+#endif /*CONFIG_CONSOLE_BTEXT */
+static void ati_ragexl_init(device_t dev)
+{
u32 chip_id;
u32 i;
int j;
u8 rev;
const char *chipname = NULL, *xtal;
int pll, mclk, xclk;
+
+#if CONFIG_CONSOLE_BTEXT==1
+
#if 0
int gtb_memsize, k;
#endif
- struct fb_info_aty *info;
- struct fb_info_aty info_t;
- struct resource *res;
- info = &info_t;
-
struct fb_var_screeninfo var;
#if 0
struct display *disp;
u8 pll_ref_div;
#endif
+#endif /*CONFIG_CONSOLE_BTEXT==1 */
+
+ struct fb_info_aty *info;
+ struct fb_info_aty info_t;
+ struct resource *res;
+ info = &info_t;
+
#define USE_AUX_REG 1
+
res = &dev->resource[0];
if(res->flags & IORESOURCE_IO) {
res = &dev->resource[1];
}
+
+#if CONFIG_CONSOLE_BTEXT==1
info->frame_buffer = res->base;
+#endif /* CONFIG_CONSOLE_BTEXT */
+
#if USE_AUX_REG==0
info->ati_regbase = res->base+0x7ff000+0xc00;
#else
}
#endif
- printk_info("ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
- info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
+#if CONFIG_CONSOLE_BTEXT==1
+ info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
+#endif
+
+#if 0
+ printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
+#endif
chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
type = chip_id & CFG_CHIP_TYPE;
rev = (chip_id & CFG_CHIP_REV)>>24;
- for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
+ for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
if (type == aty_chips[j].chip_type &&
(rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
chipname = aty_chips[j].name;
info->features = aty_chips[j].features;
goto found;
}
- printk_debug("ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
+ printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
return ;
found:
- printk_info("ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
+ printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
#if 0
if (M64_HAS(INTEGRATED)) {
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
mclk = 63;
}
#endif
+#if CONFIG_CONSOLE_BTEXT==1
aty_calc_mem_refresh(info, type, xclk);
+#endif /* CONFIG_CONSOLE_BTEXT */
+
info->pll_per = 1000000/pll;
info->mclk_per = 1000000/mclk;
info->xclk_per = 1000000/xclk;
atyfb_xl_init(info);
+#if CONFIG_CONSOLE_BTEXT==1
+
info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
info->ref_clk_per = 1000000000000ULL/14318180;
}
if (atyfb_decode_var(&var, &info->default_par, info)) {
- printk_debug("atyfb: can't set default video mode\n");
+#if 0
+ printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
+#endif
return ;
}
#if 0
}
#endif
-#if 0
+#if PLL_CRTC_DECODE==1
atyfb_set_var(&var, -1, &info->fb_info);
#else
atyfb_set_par(&info->default_par, info);
- do_install_cmap(-1, &info->fb_info);
+// do_install_cmap(-1, &info->fb_info);
+ do_install_cmap(-1, info);
#endif
-#if 0
+#if PLL_CRTC_DECODE==1
- printk_info("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
+ printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
(((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
info->current_par.crtc.bpp,
info->current_par.crtc.bpp,
info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
#else
- printk_debug("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
+ printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
(((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
info->default_par.crtc.bpp,
map_boot_text();
#if 0
- btext_drawstring("1\n");
- btext_drawstring("2\n");
- btext_drawstring("3\n");
- btext_drawstring("4\n");
- btext_drawstring("test framebuffer 5\n");
- btext_drawstring("test framebuffer 6\n");
- btext_drawstring("test framebuffer 7\n");
- btext_drawstring("test framebuffer 8\n");
- btext_drawstring("test framebuffer 9\n");
- btext_drawstring("test framebuffer 10\n");
- btext_drawstring("test framebuffer 11\n");
- btext_drawstring("test framebuffer 12\n");
- btext_drawstring("test framebuffer 13\n");
- btext_drawstring("test framebuffer 14\n");
- btext_drawstring("test framebuffer 15\n");
- btext_drawstring("test framebuffer 16\n");
- btext_drawstring("test framebuffer 17\n");
- btext_drawstring("test framebuffer 18\n");
- btext_drawstring("test framebuffer 19\n");
- btext_drawstring("test framebuffer 20\n");
- btext_drawstring("test framebuffer 21\n");
- btext_drawstring("test framebuffer 22\n");
- btext_drawstring("test framebuffer 23\n");
- btext_drawstring("test framebuffer 24\n");
+
+ btext_drawstring("test framebuffer\n");
mdelay(10000);
// test end
#endif
+
+#endif /* CONFIG_CONSOLE_BTEXT */
}
+#if CONFIG_CONSOLE_BTEXT==1
+
static int atyfb_decode_var(const struct fb_var_screeninfo *var,
struct atyfb_par *par,
const struct fb_info_aty *info)
return 0;
}
-#if 0
+#if PLL_CRTC_DECODE==1
static int atyfb_encode_var(struct fb_var_screeninfo *var,
const struct atyfb_par *par,
const struct fb_info_aty *info)
dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = 0x8080;
}
-#if 0
+#if SUPPORT_8_BPP_ABOVE==1
else if (bpp <= 16) {
bpp = 16;
pix_width = CRTC_PIX_WIDTH_15BPP;
return 0;
}
-#if 0
+#if PLL_CRTC_DECODE==1
static int aty_crtc_to_var(const struct crtc *crtc,
struct fb_var_screeninfo *var)
{
var->transp.offset = 0;
var->transp.length = 0;
break;
-#if 0
+#if SUPPORT_8_BPP_ABOVE==1
case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
bpp = 16;
var->red.offset = 10;
var->transp.offset = 0;
var->transp.length = 0;
break;
-#endif
-#if 0
case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
bpp = 16;
var->red.offset = 11;
var->transp.offset = 0;
var->transp.length = 0;
break;
-#endif
-#if 0
case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
bpp = 24;
var->red.offset = 16;
/*
* Set the User Defined Part of the Display
*/
-#if 0
+#if PLL_CRTC_DECODE==1
static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
struct fb_info *fb)
{
atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
#if 0
- printk_info("atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
+ printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
#endif
if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
return err;
#endif
- do_install_cmap(con, &info->fb_info);
+ do_install_cmap(con, info);
#if 0
}
#endif
accelmode = par->accel_flags; /* hack */
-#if 0
-// We only use default_par
+#if PLL_CRTC_DECODE==1
info->current_par = *par;
#endif
case 8:
i |= 0x02000000;
break;
-#if 0
+#if SUPPORT_8_BPP_ABOVE==1
case 16:
i |= 0x03000000;
break;
i |= info->mem_refresh_rate << 20;
switch (par->crtc.bpp) {
case 8:
-// case 24:
+#if SUPPORT_8_BPP_ABOVE==1
+ case 24:
+#endif
i |= 0x00000000;
break;
-#if 0
+#if SUPPORT_8_BPP_ABOVE==1
case 16:
i |= 0x04000000;
break;
#endif
-#if 0
- btext_update_display(info->frame_buffer_phys,
- (((par->crtc.h_tot_disp>>16) & 0xff)+1)*8,
- ((par->crtc.v_tot_disp>>16) & 0x7ff)+1,
- par->crtc.bpp,
- par->crtc.vxres*par->crtc.bpp/8);
-#endif
}
#if 0
static u16 red2[] = {
static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
- u_int transp, struct fb_info *fb)
+ u_int transp, struct fb_info_aty *info)
{
- struct fb_info_aty *info = (struct fb_info_aty *)fb;
int i, scale;
if (regno > 255)
i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
aty_st_8(DAC_CNTL, i, info);
aty_st_8(DAC_MASK, 0xff, info);
-#if 0
+#if PLL_CRTC_DECODE==1
scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
#else
scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
int fb_set_cmap(struct fb_cmap *cmap, int kspc,
int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
- struct fb_info *),
- struct fb_info *fb)
+ struct fb_info_aty *),
+ struct fb_info_aty *info)
{
int i, start;
u16 *red, *green, *blue, *transp;
blue++;
if (transp)
transp++;
- if (setcolreg(start++, hred, hgreen, hblue, htransp, fb))
+ if (setcolreg(start++, hred, hgreen, hblue, htransp, info))
return 0;
}
return 0;
return &default_16_colors;
}
-static void do_install_cmap(int con, struct fb_info *fb)
+static void do_install_cmap(int con, struct fb_info_aty *info)
{
-#if 0
- struct fb_info_aty *info = (struct fb_info_aty *)fb;
+#if PLL_CRTC_DECODE==1
int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
#else
int size = 256;
#endif
- fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, fb);
+ fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
}
+#endif /*CONFIG_CONSOLE_BTEXT */
static struct device_operations ati_ragexl_graph_ops = {
.read_resources = pci_dev_read_resources,
.scan_bus = 0,
};
-static struct pci_driver ati_ragexl_graph_driver __pci_driver = {
+static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {
.ops = &ati_ragexl_graph_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_215XL,
projects / coreboot.git / blobdiff