+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2003-2004 Linux Networx
+ * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
+ * Copyright (C) 2004 David Hendricks <sc@flagen.com>
+ * Copyright (C) 2004 Li-Ta Lo <ollie@lanl.gov>
+ * Copyright (C) 2005-2006 Tyan
+ * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
+ * Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ 2005.11 yhlu add let the real sb to use small uintid
+*/
+
#include <bitops.h>
#include <console/console.h>
#include <device/device.h>
#include <part/hard_reset.h>
#include <part/fallback_boot.h>
+#define OPT_HT_LINK 0
+
+#if OPT_HT_LINK == 1
+#include <cpu/amd/model_fxx_rev.h>
+#endif
+
static device_t ht_scan_get_devs(device_t *old_devices)
{
device_t first, last;
first = *old_devices;
last = first;
+ /* Extract the chain of devices to (first through last)
+ * for the next hypertransport device.
+ */
while(last && last->sibling &&
(last->sibling->path.type == DEVICE_PATH_PCI) &&
- (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) {
+ (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn))
+ {
last = last->sibling;
}
if (first) {
+ device_t child;
+ /* Unlink the chain from the list of old devices */
*old_devices = last->sibling;
last->sibling = 0;
+
+ /* Now add the device to the list of devices on the bus.
+ */
+ /* Find the last child of our parent */
+ for(child = first->bus->children; child && child->sibling; ) {
+ child = child->sibling;
+ }
+ /* Place the chain on the list of children of their parent. */
+ if (child) {
+ child->sibling = first;
+ } else {
+ first->bus->children = first;
+ }
}
return first;
}
+#if OPT_HT_LINK == 1
static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
{
/* Handle bugs in valid hypertransport frequency reporting */
}
/* AMD K8 Unsupported 1Ghz? */
if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
+#if K8_HT_FREQ_1G_SUPPORT == 1
+ #if K8_REV_F_SUPPORT == 0
+ if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
+ freq_cap &= ~(1 << HT_FREQ_1000Mhz);
+ }
+ #endif
+#else
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
+#endif
+
}
return freq_cap;
}
+#endif
-struct prev_link {
+struct ht_link {
struct device *dev;
unsigned pos;
- unsigned char config_off, freq_off, freq_cap_off;
+ unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
};
-static int ht_setup_link(struct prev_link *prev, device_t dev, unsigned pos)
+static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
{
static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
+ struct ht_link cur[1];
unsigned present_width_cap, upstream_width_cap;
unsigned present_freq_cap, upstream_freq_cap;
unsigned ln_present_width_in, ln_upstream_width_in;
/* Set the hypertransport link width and frequency */
reset_needed = 0;
- linkb_to_host = pci_read_config16(dev, pos + PCI_CAP_FLAGS) & (1<<10);
-
+ /* See which side of the device our previous write to
+ * set the unitid came from.
+ */
+ cur->dev = dev;
+ cur->pos = pos;
+ linkb_to_host = (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
+ if (!linkb_to_host) {
+ cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
+ cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
+ cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
+ cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
+ }
+ else {
+ cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
+ cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
+ cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
+ cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
+ }
+#if OPT_HT_LINK == 1
/* Read the capabilities */
- present_freq_cap = ht_read_freq_cap(dev, pos + (linkb_to_host ? PCI_HT_CAP_SLAVE_FREQ_CAP1: PCI_HT_CAP_SLAVE_FREQ_CAP0));
+ present_freq_cap = ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
upstream_freq_cap = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
- present_width_cap = pci_read_config8(dev, pos + (linkb_to_host ? PCI_HT_CAP_SLAVE_WIDTH1: PCI_HT_CAP_SLAVE_WIDTH0));
- upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
+ present_width_cap = pci_read_config8(cur->dev, cur->pos + cur->config_off);
+ upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
/* Calculate the highest useable frequency */
freq = log2(present_freq_cap & upstream_freq_cap);
present_width |= pow2_to_link_width[ln_upstream_width_out];
/* Set the current device */
- old_freq = pci_read_config8(dev, pos + (linkb_to_host ? PCI_HT_CAP_SLAVE_FREQ1:PCI_HT_CAP_SLAVE_FREQ0));
+ old_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
+ old_freq &= 0x0f;
if (freq != old_freq) {
- pci_write_config8(dev, pos + (linkb_to_host ? PCI_HT_CAP_SLAVE_FREQ1:PCI_HT_CAP_SLAVE_FREQ0), freq);
+ unsigned new_freq;
+ pci_write_config8(cur->dev, cur->pos + cur->freq_off, freq);
reset_needed = 1;
printk_spew("HyperT FreqP old %x new %x\n",old_freq,freq);
+ new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
+ new_freq &= 0x0f;
+ if (new_freq != freq) {
+ printk_err("%s Hypertransport frequency would not set wanted: %x got: %x\n",
+ dev_path(dev), freq, new_freq);
+ }
}
- old_width = pci_read_config8(dev, pos + (linkb_to_host ? PCI_HT_CAP_SLAVE_WIDTH1: PCI_HT_CAP_SLAVE_WIDTH0) + 1);
+ old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
if (present_width != old_width) {
- pci_write_config8(dev, pos + (linkb_to_host ? PCI_HT_CAP_SLAVE_WIDTH1: PCI_HT_CAP_SLAVE_WIDTH0) + 1, present_width);
+ unsigned new_width;
+ pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
+ present_width);
reset_needed = 1;
printk_spew("HyperT widthP old %x new %x\n",old_width, present_width);
+ new_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
+ if (new_width != present_width) {
+ printk_err("%s Hypertransport width would not set wanted: %x got: %x\n",
+ dev_path(dev), present_width, new_width);
+ }
}
/* Set the upstream device */
old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
old_freq &= 0x0f;
if (freq != old_freq) {
+ unsigned new_freq;
pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
reset_needed = 1;
printk_spew("HyperT freqU old %x new %x\n", old_freq, freq);
+ new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
+ new_freq &= 0x0f;
+ if (new_freq != freq) {
+ printk_err("%s Hypertransport frequency would not set wanted: %x got: %x\n",
+ dev_path(prev->dev), freq, new_freq);
+ }
}
old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
if (upstream_width != old_width) {
+ unsigned new_width;
pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
reset_needed = 1;
printk_spew("HyperT widthU old %x new %x\n", old_width, upstream_width);
+ new_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
+ if (new_width != upstream_width) {
+ printk_err("%s Hypertransport width would not set wanted: %x got: %x\n",
+ dev_path(prev->dev), upstream_width, new_width);
+ }
}
+#endif
- /* Remember the current link as the previous link */
- prev->dev = dev;
- prev->pos = pos;
- if(linkb_to_host) {
- prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
- prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
- prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
- }
- else {
- prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
- prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
- prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
- }
+ /* Remember the current link as the previous link,
+ * But look at the other offsets.
+ */
+ prev->dev = cur->dev;
+ prev->pos = cur->pos;
+ if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) {
+ prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
+ prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
+ prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
+ prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
+ } else {
+ prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
+ prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
+ prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
+ prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
+ }
return reset_needed;
{
unsigned pos;
pos = 0;
- switch(dev->hdr_type & 0x7f) {
- case PCI_HEADER_TYPE_NORMAL:
- case PCI_HEADER_TYPE_BRIDGE:
- pos = PCI_CAPABILITY_LIST;
- break;
- }
- if (pos > PCI_CAP_LIST_NEXT) {
- pos = pci_read_config8(dev, pos);
- }
- while(pos != 0) { /* loop through the linked list */
- uint8_t cap;
- cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
- printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
- if (cap == PCI_CAP_ID_HT) {
+ do {
+ pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
+ if (pos) {
unsigned flags;
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
- printk_spew("flags: 0x%04x\n", (unsigned)flags);
+ printk_spew("flags: 0x%04x\n", flags);
if ((flags >> 13) == 0) {
- /* Entry is a Slave secondary, success...*/
+ /* Entry is a Slave secondary, success... */
break;
}
}
- pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
- }
+ } while(pos);
return pos;
}
-static void ht_collapse_early_enumeration(struct bus *bus)
+static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_unitid)
{
unsigned int devfn;
+ struct ht_link prev;
+ unsigned ctrl;
+
+ /* Initialize the hypertransport enumeration state */
+ prev.dev = bus->dev;
+ prev.pos = bus->cap;
+ prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
+ prev.config_off = PCI_HT_CAP_HOST_WIDTH;
+ prev.freq_off = PCI_HT_CAP_HOST_FREQ;
+ prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
+
+ /* Wait until the link initialization is complete */
+ do {
+ ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+ /* Is this the end of the hypertransport chain */
+ if (ctrl & (1 << 6)) {
+ return;
+ }
+ /* Has the link failed? */
+ if (ctrl & (1 << 4)) {
+ /*
+ * Either the link has failed, or we have
+ * a CRC error.
+ * Sometimes this can happen due to link
+ * retrain, so lets knock it down and see
+ * if its transient
+ */
+ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
+ pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
+ ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+ if (ctrl & ((1 << 4) | (1 << 8))) {
+ printk_alert("Detected error on Hypertransport Link\n");
+ return;
+ }
+ }
+ } while((ctrl & (1 << 5)) == 0);
+
+ //actually, only for one HT device HT chain, and unitid is 0
+#if HT_CHAIN_UNITID_BASE == 0
+ if(offset_unitid) {
+ return;
+ }
+#endif
+
+ /* Check if is already collapsed */
+ if((!offset_unitid)|| (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) {
+ struct device dummy;
+ uint32_t id;
+ dummy.bus = bus;
+ dummy.path.type = DEVICE_PATH_PCI;
+ dummy.path.u.pci.devfn = PCI_DEVFN(0, 0);
+ id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+ if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
+ (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
+ return;
+ }
+ }
/* Spin through the devices and collapse any early
* hypertransport enumeration.
dummy.path.type = DEVICE_PATH_PCI;
dummy.path.u.pci.devfn = devfn;
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
- if (id == 0xffffffff || id == 0x00000000 ||
- id == 0x0000ffff || id == 0xffff0000) {
+ if ( (id == 0xffffffff) || (id == 0x00000000) ||
+ (id == 0x0000ffff) || (id == 0xffff0000)) {
continue;
}
-
dummy.vendor = id & 0xffff;
dummy.device = (id >> 16) & 0xffff;
dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
}
}
-unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max)
+unsigned int hypertransport_scan_chain(struct bus *bus,
+ unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid)
{
- unsigned next_unitid, last_unitid, previous_unitid;
- uint8_t previous_pos;
- device_t old_devices, dev, func, *chain_last;
- unsigned min_unitid = 1;
- int reset_needed;
- struct prev_link prev;
+ //even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
+ unsigned next_unitid, last_unitid;
+ device_t old_devices, dev, func;
+ unsigned min_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE:1;
+ struct ht_link prev;
+ device_t last_func = 0;
+ int ht_dev_num = 0;
+
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+ //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
+ unsigned real_last_unitid;
+ uint8_t real_last_pos;
+ device_t real_last_dev;
+#endif
/* Restore the hypertransport chain to it's unitialized state */
- ht_collapse_early_enumeration(bus);
+ ht_collapse_early_enumeration(bus, offset_unitid);
/* See which static device nodes I have */
old_devices = bus->children;
bus->children = 0;
- chain_last = &bus->children;
/* Initialize the hypertransport enumeration state */
- reset_needed = 0;
prev.dev = bus->dev;
prev.pos = bus->cap;
+ prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
prev.config_off = PCI_HT_CAP_HOST_WIDTH;
prev.freq_off = PCI_HT_CAP_HOST_FREQ;
prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
/* If present assign unitid to a hypertransport chain */
last_unitid = min_unitid -1;
next_unitid = min_unitid;
- previous_pos = 0;
do {
- uint32_t id, class;
- uint8_t hdr_type, pos;
+ uint8_t pos;
uint16_t flags;
unsigned count, static_count;
+ unsigned ctrl;
- previous_unitid = last_unitid;
last_unitid = next_unitid;
- /* Get setup the device_structure */
+ /* Wait until the link initialization is complete */
+ do {
+ ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+
+ if (ctrl & (1 << 6))
+ goto end_of_chain; // End of chain
+
+ if (ctrl & ((1 << 4) | (1 << 8))) {
+ /*
+ * Either the link has failed, or we have
+ * a CRC error.
+ * Sometimes this can happen due to link
+ * retrain, so lets knock it down and see
+ * if its transient
+ */
+ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
+ pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
+ ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
+ if (ctrl & ((1 << 4) | (1 << 8))) {
+ printk_alert("Detected error on Hypertransport Link\n");
+ goto end_of_chain;
+ }
+ }
+ } while((ctrl & (1 << 5)) == 0);
+
+
+ /* Get and setup the device_structure */
dev = ht_scan_get_devs(&old_devices);
- if (!dev) {
- struct device dummy;
- dummy.bus = bus;
- dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.u.pci.devfn = 0;
- id = pci_read_config32(&dummy, PCI_VENDOR_ID);
- /* If the chain is fully enumerated quit */
- if (id == 0xffffffff || id == 0x00000000 ||
- id == 0x0000ffff || id == 0xffff0000) {
- break;
- }
- dev = alloc_dev(bus, &dummy.path);
- }
- else {
- /* Add this device to the pci bus chain */
- *chain_last = dev;
- /* Run the magice enable sequence for the device */
- if (dev->chip_ops && dev->chip_ops->enable_dev) {
- dev->chip_ops->enable_dev(dev);
- }
- /* Now read the vendor and device id */
- id = pci_read_config32(dev, PCI_VENDOR_ID);
-
- /* If the chain is fully enumerated quit */
- if (id == 0xffffffff || id == 0x00000000 ||
- id == 0x0000ffff || id == 0xffff0000) {
- if (dev->enabled) {
- printk_info("Disabling static device: %s\n",
- dev_path(dev));
- dev->enabled = 0;
- }
- break;
- }
- }
- /* Update the device chain tail */
- for(func = dev; func; func = func->sibling) {
- chain_last = &func->sibling;
+ /* See if a device is present and setup the
+ * device structure.
+ */
+ dev = pci_probe_dev(dev, bus, 0);
+ if (!dev || !dev->enabled) {
+ break;
}
-
- /* Read the rest of the pci configuration information */
- hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
- class = pci_read_config32(dev, PCI_CLASS_REVISION);
-
- /* Store the interesting information in the device structure */
- dev->vendor = id & 0xffff;
- dev->device = (id >> 16) & 0xffff;
- dev->hdr_type = hdr_type;
- /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
- dev->class = class >> 8;
/* Find the hypertransport link capability */
pos = ht_lookup_slave_capability(dev);
break;
}
-
/* Update the Unitid of the current device */
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
+
+ /* If the devices has a unitid set and is at devfn 0 we are done.
+ * This can happen with shadow hypertransport devices,
+ * or if we have reached the bottom of a
+ * hypertransport device chain.
+ */
+ if (flags & 0x1f) {
+ break;
+ }
+
flags &= ~0x1f; /* mask out base Unit ID */
- flags |= next_unitid & 0x1f;
- pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+ flags |= next_unitid & 0x1f;
+ pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
/* Update the Unitd id in the device structure */
static_count = 1;
func->path.u.pci.devfn += (next_unitid << 3);
static_count = (func->path.u.pci.devfn >> 3)
- (dev->path.u.pci.devfn >> 3) + 1;
+ last_func = func;
}
/* Compute the number of unitids consumed */
}
/* Update the Unitid of the next device */
+ ht_unitid_base[ht_dev_num] = next_unitid;
+ ht_dev_num++;
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+ if(offset_unitid) {
+ real_last_unitid = next_unitid;
+ real_last_pos = pos;
+ real_last_dev = dev;
+ }
+#endif
next_unitid += count;
/* Setup the hypetransport link */
- reset_needed |= ht_setup_link(&prev, dev, pos);
+ bus->reset_needed |= ht_setup_link(&prev, dev, pos);
printk_debug("%s [%04x/%04x] %s next_unitid: %04x\n",
dev_path(dev),
dev->vendor, dev->device,
(dev->enabled? "enabled": "disabled"), next_unitid);
- } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
-#if HAVE_HARD_RESET == 1
- if(reset_needed) {
+ } while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3)));
+ end_of_chain:
+#if OPT_HT_LINK == 1
+ if(bus->reset_needed) {
printk_info("HyperT reset needed\n");
- hard_reset();
}
else {
printk_debug("HyperT reset not needed\n");
}
#endif
+
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+ if(offset_unitid && (ht_dev_num>0)) {
+ uint16_t flags;
+ int i;
+ device_t last_func = 0;
+ flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
+ flags &= ~0x1f;
+ flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
+ pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
+
+ for(func = real_last_dev; func; func = func->sibling) {
+ func->path.u.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3);
+ last_func = func;
+ }
+
+ ht_unitid_base[ht_dev_num-1] = HT_CHAIN_END_UNITID_BASE; // update last one
+
+ next_unitid = real_last_unitid;
+ }
+#endif
+
if (next_unitid > 0x1f) {
next_unitid = 0x1f;
}
- return pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max);
+
+ /* Die if any leftover Static devices are are found.
+ * There's probably a problem in the Config.lb.
+ */
+ if(old_devices) {
+ device_t left;
+ for(left = old_devices; left; left = left->sibling) {
+ printk_debug("%s\n", dev_path(left));
+ }
+ printk_err("HT: Left over static devices. Check your Config.lb\n");
+ if(last_func && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it
+ last_func->sibling = old_devices;
+ }
+
+ /* Now that nothing is overlapping it is safe to scan the
+ * children.
+ */
+ max = pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max);
+ return max;
}
+
+/**
+ * @brief Scan a PCI bridge and the buses behind the bridge.
+ *
+ * Determine the existence of buses behind the bridge. Set up the bridge
+ * according to the result of the scan.
+ *
+ * This function is the default scan_bus() method for PCI bridge devices.
+ *
+ * @param dev pointer to the bridge device
+ * @param max the highest bus number assgined up to now
+ *
+ * @return The maximum bus number found, after scanning all subordinate busses
+ */
+unsigned int hypertransport_scan_chain_x(struct bus *bus,
+ unsigned min_devfn, unsigned max_devfn, unsigned int max)
+{
+ unsigned ht_unitid_base[4];
+ unsigned offset_unitid = 1;
+ return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid);
+}
+
+unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
+{
+ return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x);
+}
+
+
+/** Default device operations for hypertransport bridges */
+static struct pci_operations ht_bus_ops_pci = {
+ .set_subsystem = 0,
+};
+
+struct device_operations default_ht_ops_bus = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = 0,
+ .scan_bus = ht_scan_bridge,
+ .enable = 0,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &ht_bus_ops_pci,
+};