SMM for AMD K8 Part 1/2

[coreboot.git] / src / cpu / x86 / smm / smmrelocate.S

diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index fa94b881139eb49fc1870724f16375bfd00d18b3..e477830cf1c84863326ba88677756c871740bd83 100644 (file)
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2010 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,17 +19,24 @@
  * MA 02110-1301 USA
  */
 
-#include <arch/asm.h>
-
 // Make sure no stage 2 code is included:
 #define __PRE_RAM__
 
-// FIXME: Is this piece of code southbridge specific, or 
+#if !defined(CONFIG_NORTHBRIDGE_AMD_AMDK8) && !defined(CONFIG_NORTHBRIDGE_AMD_FAM10)
+
+// FIXME: Is this piece of code southbridge specific, or
 // can it be cleaned up so this include is not required?
+// It's needed right now because we get our DEFAULT_PMBASE from
+// here.
+#if defined(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
 #include "../../../southbridge/intel/i82801gx/i82801gx.h"
-
-#undef DEBUG_SMM_RELOCATION
-//#define DEBUG_SMM_RELOCATION
+#elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
+#include "../../../southbridge/intel/i82801dx/i82801dx.h"
+#elif defined(CONFIG_SOUTHBRIDGE_INTEL_SCH)
+#include "../../../southbridge/intel/sch/sch.h"
+#else
+#error "Southbridge needs SMM handler support."
+#endif
 
 #define LAPIC_ID 0xfee00020
 
@@ -73,7 +80,7 @@
  * 0xa0000-0xa0400 and the stub plus stack would need to go
  * at 0xa8000-0xa8100 (example for core 0). That is not enough.
  *
- * This means we're basically limited to 16 cpu cores before 
+ * This means we're basically limited to 16 cpu cores before
  * we need to use the TSEG/HSEG for the actual SMM handler plus stack.
  * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
  *
@@ -101,7 +108,7 @@ smm_relocation_start:
        addr32 mov (%ebx), %al
        cmp $0x64, %al
        je 1f
- 
+
        mov $0x38000 + 0x7ef8, %ebx
        jmp smm_relocate
 1:
@@ -112,8 +119,8 @@ smm_relocate:
        movl $LAPIC_ID, %esi
        addr32 movl (%esi), %ecx
        shr  $24, %ecx
-       
-       /* calculate offset by multiplying the 
+
+       /* calculate offset by multiplying the
         * apic ID by 1024 (0x400)
         */
        movl %ecx, %edx
@@ -125,7 +132,7 @@ smm_relocate:
        addr32 movl %eax, (%ebx)
 
 
-       /* The next section of code is hardware specific */
+       /* The next section of code is potentially southbridge specific */
 
        /* Clear SMI status */
        movw $(DEFAULT_PMBASE + 0x34), %dx
@@ -143,8 +150,9 @@ smm_relocate:
        orl $(1 << 1), %eax
        outl %eax, %dx
 
-       /* End of hardware specific section. */
-#ifdef DEBUG_SMM_RELOCATION
+       /* End of southbridge specific section. */
+
+#if defined(CONFIG_DEBUG_SMM_RELOCATION) && CONFIG_DEBUG_SMM_RELOCATION
        /* print [SMM-x] so we can determine if CPUx went to SMM */
        movw $CONFIG_TTYS0_BASE, %dx
        mov $'[', %al
@@ -158,7 +166,7 @@ smm_relocate:
        outb %al, %dx
        /* calculate ascii of cpu number. More than 9 cores? -> FIXME */
        movb %cl, %al
-       addb $'0', %al 
+       addb $'0', %al
        outb %al, %dx
        mov $']', %al
        outb %al, %dx
@@ -171,4 +179,4 @@ smm_relocate:
        /* That's it. return */
        rsm
 smm_relocation_end:
-
+#endif