Add support to run SMM handler in TSEG instead of ASEG

[coreboot.git] / src / cpu / x86 / smm / smihandler.c

diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 00cae1005f9133d3646e46852bb17e73b1beabc6..bbed0f195ef9bd0954d4ecf3b690e44f433097f9 100644 (file)
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -25,12 +25,11 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
-void southbridge_smi_set_eos(void);
-
+#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
 
 /* SMI multiprocessing semaphore */
-static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED;
+static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED;
 
 static int smi_obtain_lock(void)
 {
@@ -48,7 +47,7 @@ static int smi_obtain_lock(void)
        return (ret == SMI_UNLOCKED);
 }
 
-static void smi_release_lock(void)
+void smi_release_lock(void)
 {
        asm volatile (
                "movb %1, %%al\n"
@@ -58,6 +57,7 @@ static void smi_release_lock(void)
                : "eax"
        );
 }
+#endif
 
 #define LAPIC_ID 0xfee00020
 static inline __attribute__((always_inline)) unsigned long nodeid(void)
@@ -70,7 +70,7 @@ void io_trap_handler(int smif)
        /* If a handler function handled a given IO trap, it
         * shall return a non-zero value
         */
-        printk_debug("SMI function trap 0x%x: ", smif);
+        printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
 
        if (southbridge_io_trap_handler(smif))
                return;
@@ -78,7 +78,7 @@ void io_trap_handler(int smif)
        if (mainboard_io_trap_handler(smif))
                return;
 
-       printk_debug("Unknown function\n");
+       printk(BIOS_DEBUG, "Unknown function\n");
 }
 
 /**
@@ -89,6 +89,24 @@ static void smi_set_eos(void)
        southbridge_smi_set_eos();
 }
 
+static u32 pci_orig;
+
+/**
+ * @brief Backup PCI address to make sure we do not mess up the OS
+ */
+static void smi_backup_pci_address(void)
+{
+       pci_orig = inl(0xcf8);
+}
+
+/**
+ * @brief Restore PCI address previously backed up
+ */
+static void smi_restore_pci_address(void)
+{
+       outl(pci_orig, 0xcf8);
+}
+
 /**
  * @brief Interrupt handler for SMI#
  *
@@ -100,20 +118,28 @@ void smi_handler(u32 smm_revision)
        unsigned int node;
        smm_state_save_area_t state_save;
 
+#if !CONFIG_SMM_TSEG
        /* Are we ok to execute the handler? */
        if (!smi_obtain_lock()) {
                /* For security reasons we don't release the other CPUs
                 * until the CPU with the lock is actually done
                 */
-               while (smi_handler_status == SMI_LOCKED) /* wait */ ;
+               while (smi_handler_status == SMI_LOCKED) {
+                       asm volatile (
+                               ".byte 0xf3, 0x90\n"  /* hint a CPU we are in spinlock (PAUSE instruction, REP NOP) */
+                       );
+               }
                return;
        }
+#endif
+
+       smi_backup_pci_address();
 
        node=nodeid();
 
        console_init();
 
-       printk_spew("\nSMI# #%d\n", node);
+       printk(BIOS_SPEW, "\nSMI# #%d\n", node);
 
        switch (smm_revision) {
        case 0x00030002:
@@ -123,6 +149,7 @@ void smi_handler(u32 smm_revision)
                        (0xa8000 + 0x7e00 - (node * 0x400));
                break;
        case 0x00030100:
+       case 0x00030101: /* SandyBridge */
                state_save.type = EM64T;
                state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
                        (0xa8000 + 0x7d00 - (node * 0x400));
@@ -133,8 +160,8 @@ void smi_handler(u32 smm_revision)
                        (0xa8000 + 0x7e00 - (node * 0x400));
                break;
        default:
-               printk_debug("smm_revision: 0x%08x\n", smm_revision);
-               printk_debug("SMI# not supported on your CPU\n");
+               printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
+               printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
                /* Don't release lock, so no further SMI will happen,
                 * if we don't handle it anyways.
                 */
@@ -149,7 +176,11 @@ void smi_handler(u32 smm_revision)
        if (southbridge_smi_handler)
                southbridge_smi_handler(node, &state_save);
 
+       smi_restore_pci_address();
+
+#if !CONFIG_SMM_TSEG
        smi_release_lock();
+#endif
 
        /* De-assert SMI# signal to allow another SMI */
        smi_set_eos();