printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / cpu / x86 / smm / smihandler.c

diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 0dc8926653df18ddce8ae85d2411629d8e97739c..3dddf6c8ae7d5ff6340b5174201fb94d1230bf99 100644 (file)
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -25,10 +25,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
-void southbridge_smi_set_eos(void);
-
-#define DEBUG_SMI
-
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
 
 /* SMI multiprocessing semaphore */
@@ -67,69 +63,20 @@ static inline __attribute__((always_inline)) unsigned long nodeid(void)
        return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
 }
 
-/* ********************* smi_util ************************* */
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-static int uart_can_tx_byte(void)
-{
-       return inb(TTYS0_BASE + UART_LSR) & 0x20;
-}
-
-static void uart_wait_to_tx_byte(void)
-{
-       while(!uart_can_tx_byte()) 
-       ;
-}
-
-static void uart_wait_until_sent(void)
-{
-       while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
-       ; 
-}
-
-static void uart_tx_byte(unsigned char data)
-{
-       uart_wait_to_tx_byte();
-       outb(data, TTYS0_BASE + UART_TBR);
-       /* Make certain the data clears the fifos */
-       uart_wait_until_sent();
-}
-
-void console_tx_flush(void)
-{
-       uart_wait_to_tx_byte();
-}
-
-void console_tx_byte(unsigned char byte)
+void io_trap_handler(int smif)
 {
-       if (byte == '\n')
-               uart_tx_byte('\r');
-       uart_tx_byte(byte);
-}
+       /* If a handler function handled a given IO trap, it
+        * shall return a non-zero value
+        */
+        printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
 
-/* ********************* smi_util ************************* */
+       if (southbridge_io_trap_handler(smif))
+               return;
 
+       if (mainboard_io_trap_handler(smif))
+               return;
 
-void io_trap_handler(int smif)
-{
-       southbridge_io_trap_handler(smif);
+       printk(BIOS_DEBUG, "Unknown function\n");
 }
 
 /**
@@ -148,28 +95,26 @@ static void smi_set_eos(void)
 
 void smi_handler(u32 smm_revision)
 {
-       u8 reg8;
-       u16 pmctrl;
-       u16 pm1_sts;
-       u32 smi_sts, gpe0_sts, tco_sts;
        unsigned int node;
        smm_state_save_area_t state_save;
 
        /* Are we ok to execute the handler? */
-       if (!smi_obtain_lock())
+       if (!smi_obtain_lock()) {
+               /* For security reasons we don't release the other CPUs
+                * until the CPU with the lock is actually done
+                */
+               while (smi_handler_status == SMI_LOCKED) /* wait */ ;
                return;
+       }
 
        node=nodeid();
 
-#ifdef DEBUG_SMI
-       console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
-#else
-       console_loglevel = 1;
-#endif
+       console_init();
 
-       printk_debug("\nSMI# #%d\n", node);
+       printk(BIOS_SPEW, "\nSMI# #%d\n", node);
 
        switch (smm_revision) {
+       case 0x00030002:
        case 0x00030007:
                state_save.type = LEGACY;
                state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
@@ -186,15 +131,21 @@ void smi_handler(u32 smm_revision)
                        (0xa8000 + 0x7e00 - (node * 0x400));
                break;
        default:
-               printk_debug("smm_revision: 0x%08x\n", smm_revision);
-               printk_debug("SMI# not supported on your CPU\n");
+               printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
+               printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
                /* Don't release lock, so no further SMI will happen,
                 * if we don't handle it anyways.
                 */
                return;
        }
 
-       southbridge_smi_handler(node, &state_save);
+       /* Call chipset specific SMI handlers. */
+       if (cpu_smi_handler)
+               cpu_smi_handler(node, &state_save);
+       if (northbridge_smi_handler)
+               northbridge_smi_handler(node, &state_save);
+       if (southbridge_smi_handler)
+               southbridge_smi_handler(node, &state_save);
 
        smi_release_lock();