Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / cpu / x86 / mtrr / earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 74e0a64dcea92c67e00456c897891127fa33d80f..1cbc5443504a05a602da3e66010e49478c743271 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -2,36 +2,10 @@
 #define EARLYMTRR_C
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
-#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
-# error "XIP_ROM_SIZE without XIP_ROM_BASE"
-#endif
-#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
-# error "XIP_ROM_BASE without XIP_ROM_SIZE"
-#endif
-#if !defined(CONFIG_LB_MEM_TOPK)
-# error "CONFIG_LB_MEM_TOPK not defined"
-#endif
-
-#if __ROMCC__  == 0 && __ROMCC_MINOR__ <= 64
-
-#warning "Not checking if XIP_ROM_SIZE is valid to avoid romcc preprocessor deficiency"
-
-#else
-# if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
-#  error "XIP_ROM_SIZE is not a power of 2"
-# endif
-# if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
-#  error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
-# endif
-#endif
-
-#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
-# error "CONFIG_LB_MEM_TOPK must be a power of 2"
-#endif
-
+#if 0
 static void disable_var_mtrr(unsigned reg)
 {
        /* The invalid bit is kept in the mask so we simply
@@ -42,30 +16,52 @@ static void disable_var_mtrr(unsigned reg)
        zero.lo = zero.hi = 0;
        wrmsr(MTRRphysMask_MSR(reg), zero);
 }
+#endif
 
 static void set_var_mtrr(
        unsigned reg, unsigned base, unsigned size, unsigned type)
 
 {
        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+       /* FIXME: It only support 4G less range */
        msr_t basem, maskm;
        basem.lo = base | type;
        basem.hi = 0;
        wrmsr(MTRRphysBase_MSR(reg), basem);
        maskm.lo = ~(size - 1) | 0x800;
-       maskm.hi = 0x0f;
+       maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
-static void cache_lbmem(int type)
+#if 0
+static void set_var_mtrr_x(
+        unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
+
+{
+        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+        msr_t basem, maskm;
+        basem.lo = (base_lo & 0xfffff000) | type;
+        basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
+        wrmsr(MTRRphysBase_MSR(reg), basem);
+               maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
+       if(size_lo) {
+               maskm.lo = ~(size_lo - 1) | 0x800;
+       } else {
+               maskm.lo = 0x800;
+               maskm.hi &= ~(size_hi - 1);
+       }
+        wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+#endif
+
+static inline void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
        disable_cache();
-       set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type);
+       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type);
        enable_cache();
 }
 
-
 /* the fixed and variable MTTRs are power-up with random values,
  * clear them to MTRR_TYPE_UNCACHEABLE for safty.
  */
@@ -77,9 +73,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
         */
        msr_t msr;
        const unsigned long *msr_addr;
-       unsigned long cr0;
-
-       print_spew("Clearing mtrr\r\n");
 
        /* Inialize all of the relevant msrs to 0 */
        msr.lo = 0;
@@ -89,23 +82,23 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
                wrmsr(msr_nr, msr);
        }
 
-#if defined(XIP_ROM_SIZE)
+#if defined(CONFIG_XIP_ROM_SIZE)
        /* enable write through caching so we can do execute in place
         * on the flash rom.
         */
-       set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+       set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
-       /* Set the default memory type and enable fixed and variable MTRRs 
+       /* Set the default memory type and enable fixed and variable MTRRs
         */
        /* Enable Variable MTRRs */
        msr.hi = 0x00000000;
        msr.lo = 0x00000800;
        wrmsr(MTRRdefType_MSR, msr);
-       
+
 }
 
-static void early_mtrr_init(void)
+static inline void early_mtrr_init(void)
 {
        static const unsigned long mtrr_msrs[] = {
                /* fixed mtrr */
@@ -126,4 +119,17 @@ static void early_mtrr_init(void)
        enable_cache();
 }
 
+static inline int early_mtrr_init_detected(void)
+{
+       msr_t msr;
+       /* See if MTRR's are enabled.
+        * a #RESET disables them while an #INIT
+        * preserves their state.  This works
+        * on both Intel and AMD cpus, at least
+        * according to the documentation.
+        */
+       msr = rdmsr(MTRRdefType_MSR);
+       return msr.lo & 0x00000800;
+}
+
 #endif /* EARLYMTRR_C */