Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / cpu / x86 / mtrr / earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 150091e7a860d00664d7c058579d3f5592c397bd..1cbc5443504a05a602da3e66010e49478c743271 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -2,30 +2,10 @@
 #define EARLYMTRR_C
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
-# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
-#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
-
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
+#if 0
 static void disable_var_mtrr(unsigned reg)
 {
        /* The invalid bit is kept in the mask so we simply
@@ -36,6 +16,7 @@ static void disable_var_mtrr(unsigned reg)
        zero.lo = zero.hi = 0;
        wrmsr(MTRRphysMask_MSR(reg), zero);
 }
+#endif
 
 static void set_var_mtrr(
        unsigned reg, unsigned base, unsigned size, unsigned type)
@@ -52,6 +33,7 @@ static void set_var_mtrr(
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+#if 0
 static void set_var_mtrr_x(
         unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
 
@@ -70,8 +52,9 @@ static void set_var_mtrr_x(
        }
         wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
+#endif
 
-static void cache_lbmem(int type)
+static inline void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
        disable_cache();
@@ -100,28 +83,22 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
        }
 
 #if defined(CONFIG_XIP_ROM_SIZE)
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-extern unsigned long AUTO_XIP_ROM_BASE;
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
        /* enable write through caching so we can do execute in place
         * on the flash rom.
         */
        set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
-       /* Set the default memory type and enable fixed and variable MTRRs 
+       /* Set the default memory type and enable fixed and variable MTRRs
         */
        /* Enable Variable MTRRs */
        msr.hi = 0x00000000;
        msr.lo = 0x00000800;
        wrmsr(MTRRdefType_MSR, msr);
-       
+
 }
 
-static void early_mtrr_init(void)
+static inline void early_mtrr_init(void)
 {
        static const unsigned long mtrr_msrs[] = {
                /* fixed mtrr */
@@ -142,7 +119,7 @@ static void early_mtrr_init(void)
        enable_cache();
 }
 
-static int early_mtrr_init_detected(void)
+static inline int early_mtrr_init_detected(void)
 {
        msr_t msr;
        /* See if MTRR's are enabled.