AMD Rev F support

[coreboot.git] / src / cpu / x86 / mtrr / earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index c435b2edd56bc08f5e5ab12e2840aa888a236f47..1c00bd7dcce747dba20e890673e89bf1ccfc8e56 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -37,8 +37,8 @@ static void disable_var_mtrr(unsigned reg)
        wrmsr(MTRRphysMask_MSR(reg), zero);
 }
 
-static void set_var_mtrr(unsigned reg, unsigned base, unsigned size,
-                        unsigned type)
+static void set_var_mtrr(
+       unsigned reg, unsigned base, unsigned size, unsigned type)
 
 {
        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
@@ -47,10 +47,29 @@ static void set_var_mtrr(unsigned reg, unsigned base, unsigned size,
        basem.hi = 0;
        wrmsr(MTRRphysBase_MSR(reg), basem);
        maskm.lo = ~(size - 1) | 0x800;
-       maskm.hi = 0x0f;
+       maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+static void set_var_mtrr_x(
+        unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
+
+{
+        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+        msr_t basem, maskm;
+        basem.lo = (base_lo & 0xfffff000) | type;
+        basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
+        wrmsr(MTRRphysBase_MSR(reg), basem);
+               maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
+       if(size_lo) {
+               maskm.lo = ~(size_lo - 1) | 0x800;
+       } else {
+               maskm.lo = 0x800;
+               maskm.hi &= ~(size_hi - 1);
+       }
+        wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
 static void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
@@ -70,13 +89,12 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
         */
        msr_t msr;
        const unsigned long *msr_addr;
-       unsigned long cr0;
 
        /* Inialize all of the relevant msrs to 0 */
        msr.lo = 0;
        msr.hi = 0;
        unsigned long msr_nr;
-       for (msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
+       for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
                wrmsr(msr_nr, msr);
        }
 
@@ -117,4 +135,17 @@ static void early_mtrr_init(void)
        enable_cache();
 }
 
+static int early_mtrr_init_detected(void)
+{
+       msr_t msr;
+       /* See if MTRR's are enabled.
+        * a #RESET disables them while an #INIT
+        * preserves their state.  This works
+        * on both Intel and AMD cpus, at least
+        * according to the documentation.
+        */
+       msr = rdmsr(MTRRdefType_MSR);
+       return msr.lo & 0x00000800;
+}
+
 #endif /* EARLYMTRR_C */