MTRR: get physical address size from CPUID

[coreboot.git] / src / cpu / intel / model_f2x / model_f2x_init.c

diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index 607de0bccf47e9202c932dd6b168c1ed9470e55b..ec78672de648534bf83f3913feaedccac44c82b4 100644 (file)
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -1,6 +1,5 @@
 #include <console/console.h>
 #include <device/device.h>
-#include <device/device.h>
 #include <device/pci.h>
 #include <string.h>
 #include <cpu/cpu.h>
@@ -8,8 +7,8 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 
 /* 512KB cache */
 static uint32_t microcode_updates[] = {
@@ -17,11 +16,27 @@ static uint32_t microcode_updates[] = {
         * microcode update lengths.  They are encoded in int 8 and 9.  A
         * dummy header of nulls must terminate the list.
         */
+
+       /* Old microcode file not present in Intel's microcode.dat. */
 #include "microcode_m02f2203.h"
-#include "microcode_m02f2410.h"
-//#include "microcode_m02f2728.h"
-#include "microcode_m02f2734.h"
-#include "microcode_m02f2918.h"
+
+       /* files from Intel's microcode.dat */
+#include "microcode-1343-m04f252b.h"
+#include "microcode-1346-m10f252c.h"
+#include "microcode-1338-m02f292d.h"
+#include "microcode-1340-m08f292f.h"
+#include "microcode-1107-m10f2421.h"
+#include "microcode-1339-m04f292e.h"
+#include "microcode-1105-m08f2420.h"
+#include "microcode-1336-m02f2610.h"
+#include "microcode-1101-m02f2738.h"
+#include "microcode-1100-m04f2737.h"
+#include "microcode-1341-m01f2529.h"
+#include "microcode-1102-m08f2739.h"
+#include "microcode-1104-m04f241e.h"
+#include "microcode-1342-m02f252a.h"
+#include "microcode-1106-m02f241f.h"
+
        /*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
         0x0, 0x0, 0x0, 0x0,
@@ -29,14 +44,13 @@ static uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-
 static void model_f2x_init(device_t cpu)
 {
        /* Turn on caching if we haven't already */
        x86_enable_cache();
-       x86_setup_mtrrs(36);
+       x86_setup_mtrrs();
        x86_mtrr_check();
-       
+
        /* Update the microcode */
        intel_update_microcode(microcode_updates);
 
@@ -50,12 +64,14 @@ static void model_f2x_init(device_t cpu)
 static struct device_operations cpu_dev_ops = {
        .init     = model_f2x_init,
 };
+
 static struct cpu_device_id cpu_table[] = {
        { X86_VENDOR_INTEL, 0x0f22 },
        { X86_VENDOR_INTEL, 0x0f24 },
+       { X86_VENDOR_INTEL, 0x0f25 },
+       { X86_VENDOR_INTEL, 0x0f26 },
        { X86_VENDOR_INTEL, 0x0f27 },
        { X86_VENDOR_INTEL, 0x0f29 },
-//     { X86_VENDOR_INTEL, 0x0f25 }, /* I don't have a microcode update for this cpu */
        { 0, 0 },
 };