printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / cpu / intel / model_6fx / model_6fx_init.c

diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index d716efbd483eea31d4838f9d85a2b96407c5b5a2..f00aba8e33fa153a887cf57e416806d398327dff 100644 (file)
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -34,23 +34,23 @@
 #include <usbdebug_direct.h>
 
 static const uint32_t microcode_updates[] = {
-       #include "microcode-2127-m206f6c7.h"
        #include "microcode-2129-m206f257.h"
        #include "microcode-2334-m016fbB6.h"
-       #include "microcode-2335-m086fbB6.h"
        #include "microcode-2336-m106fbB6.h"
        #include "microcode-2337-m806fbB6.h"
-       #include "microcode-2339-m046fbB7.h"
-       #include "microcode-2340-m406fbB7.h"
        #include "microcode-2346-m16fda3.h"
        #include "microcode-2347-m206fda3.h"
        #include "microcode-2348-m806fda3.h"
        #include "microcode-2374-m16f6cb.h"
+       #include "microcode-2375-m206f6cc.h"
        #include "microcode-2376-m46f6cd.h"
        #include "microcode-2380-m106f768.h"
        #include "microcode-2381-m406f769.h"
        #include "microcode-2385-m806fa94.h"
        #include "microcode-2389-m16f25a.h"
+       #include "microcode-2986-m086fbB8.h"
+       #include "microcode-2990-m046fbB9.h"
+       #include "microcode-2991-m406fbB9.h"
        /*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
         0x0, 0x0, 0x0, 0x0,
@@ -126,9 +126,16 @@ static void enable_vmx(void)
 #define PMG_IO_BASE_ADDR       0xe3
 #define PMG_IO_CAPTURE_ADDR    0xe4
 
-#define PMB0_BASE              0x580
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE              0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
 #define PMB1_BASE              0x800
-#define CST_RANGE              2
+#define HIGHEST_CLEVEL         3
 static void configure_c_states(void)
 {
        msr_t msr;
@@ -141,6 +148,10 @@ static void configure_c_states(void)
        msr.lo &= ~(1 << 9); // Issue a  single stop grant cycle upon stpclk
        msr.lo |= (1 << 3); // Dynamic L2
 
+        /* Number of supported C-States */
+       msr.lo &= ~7;
+       msr.lo |= HIGHEST_CLEVEL; // support at most C3
+
        wrmsr(PMG_CST_CONFIG_CONTROL, msr);
 
        /* Set Processor MWAIT IO BASE */
@@ -148,9 +159,9 @@ static void configure_c_states(void)
        msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
        wrmsr(PMG_IO_BASE_ADDR, msr);
 
-       /* Set IO Capture Address */
+       /* Set C_LVL controls and IO Capture Address */
        msr.hi = 0;
-       msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16);
+       msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
        wrmsr(PMG_IO_CAPTURE_ADDR, msr);
 }
 
@@ -216,7 +227,7 @@ static void model_6fx_init(device_t cpu)
 
        /* Print processor name */
        fill_processor_name(processor_name);
-       printk_info("CPU: %s.\n", processor_name);
+       printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
 #if CONFIG_USBDEBUG_DIRECT
        // Is this caution really needed?
@@ -229,6 +240,9 @@ static void model_6fx_init(device_t cpu)
        x86_setup_mtrrs(36);
        x86_mtrr_check();
 
+       /* Setup Page Attribute Tables (PAT) */
+       // TODO set up PAT
+
 #if CONFIG_USBDEBUG_DIRECT
        set_ehci_debug(ehci_debug_addr);
 #endif
@@ -264,6 +278,7 @@ static struct cpu_device_id cpu_table[] = {
        { X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */
        { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */
        { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */
+       { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */
        { 0, 0 },
 };