MTRR: get physical address size from CPUID

[coreboot.git] / src / cpu / intel / model_6fx / model_6fx_init.c

diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index c43b8debb1f513d42148f2c6e5e44bbd0400bcac..033dfe6639ef78c1f83582d8347b127e01062f77 100644 (file)
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -28,9 +28,10 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/acpi.h>
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/name.h>
 #include <usbdebug.h>
 
@@ -95,15 +96,6 @@ static void enable_vmx(void)
 #define PMG_IO_BASE_ADDR       0xe3
 #define PMG_IO_CAPTURE_ADDR    0xe4
 
-/* MWAIT coordination I/O base address. This must match
- * the \_PR_.CPU0 PM base address.
- */
-#define PMB0_BASE              0x510
-
-/* PMB1: I/O port that triggers SMI once cores are in the same state.
- * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
- */
-#define PMB1_BASE              0x800
 #define HIGHEST_CLEVEL         3
 static void configure_c_states(void)
 {
@@ -165,6 +157,19 @@ static void configure_misc(void)
 
        msr.lo |= (1 << 20);    /* Lock Enhanced SpeedStep Enable */
        wrmsr(IA32_MISC_ENABLE, msr);
+
+       // set maximum CPU speed
+       msr = rdmsr(IA32_PERF_STS);
+       int busratio_max=(msr.hi >> (40-32)) & 0x1f;
+
+       msr = rdmsr(IA32_PLATFORM_ID);
+       int vid_max=msr.lo & 0x3f;
+
+       msr.lo &= ~0xffff;
+       msr.lo |= busratio_max << 8;
+       msr.lo |= vid_max;
+
+       wrmsr(IA32_PERF_CTL, msr);
 }
 
 #define PIC_SENS_CFG   0x1aa
@@ -206,7 +211,7 @@ static void model_6fx_init(device_t cpu)
 #endif
 
        /* Setup MTRRs */
-       x86_setup_mtrrs(36);
+       x86_setup_mtrrs();
        x86_mtrr_check();
 
        /* Setup Page Attribute Tables (PAT) */